A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

Abstract

Abstract-Nowadays, multi-core systems-on-chip (SoCs) are typically required to execute multiple complex applications, which demand a large set of heterogeneous hardware cores with different sizes. In this context, the popularity of dynamically reconfigurable platforms is growing, as they increase the ability of the initial design to adapt to future modifications. This paper presents a design flow to efficiently map multiple multi-core applications on a dynamically reconfigurable SoC. The proposed methodology is tailored for a reconfigurable hardware architecture based on a flexible communication infrastructure, and exploits applications similarities to obtain an effective mapping. We also introduce a run-time mapper that is able to introduce new applications that were not known at design-time, preserving the mapping of the original system. We apply our design flow to a real-world multimedia case study and to a set of synthetic benchmarks, showing that it is actually able to extract similarities among the applications, as it achieves an average improvement of 29% in terms of reconfiguration latency with respect to a communication-oriented approach, while preserving the same communication performance.Index Terms-Field programmable gate arrays, platformbased design, reconfigurable architectures, run-time adaptability.

A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms

“…Our experimental results show that the proposed approach achieves up to 75% of resources saving and up to 89% reduction in terms of reconfiguration overhead with respect to other representative state-of-the-art approaches [Murali et al 2006a;Beretta et al 2011b;Clemente et al 2011b]. In addition, we illustrate how our approach can be applied to actual multimedia applications [Theelen et al 2008;Taghipour et al 2008;Verderber et al 2003;Janiaut et al 2005;Roitzsch 2007;Lindroth et al 2006;Mei-hua et al 2007] running on a real system developed on a Xilinx TM Virtex-5 FPGA.…”

“…However, task mapping for DFDs has been extensively studied in the literature for complex SoCs. Three relevant related works in the context of reconfigurable systems are Murali et al [2006b], Hansson [2005], and Beretta et al [2011b]. The approaches presented in these first two works aim at minimizing the area requirements and area consumption in the deployment of the tasks of a sole DFD in the target SoC.…”

“…In addition, we illustrate how our approach can be applied to actual multimedia applications [Theelen et al 2008;Taghipour et al 2008;Verderber et al 2003;Janiaut et al 2005;Roitzsch 2007;Lindroth et al 2006;Mei-hua et al 2007] running on a real system developed on a Xilinx TM Virtex-5 FPGA. With respect to other state-of-the-art approaches [Beretta et al 2011b;Clemente et al 2011a], we hereby introduce our contributions.…”

Mapeamento e posicionamento de módulos processantes em sistemas dinamicamente reconfiguráveis baseados em redes intrachip.

“…Entre eles pode-se citar (RANA et al, 2009;BERETTA et al, 2010, BERETTA et al, 2011 Apesar destes trabalhos abordarem o problema de mapeamento em SDRs, estes possuem uma abordagem multitarefas, utilizando uma arquitetura específica, que não pode ser aplicadas nas arquiteturas NoC-SDRs complexas apresentadas na seção 2.6.…”

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

“…Since the static approaches are inherently non-scalable and limited in the ability to provide high performance in cases where the traffic characteristics vary dynamically, a number of automatic designs were proposed to dynamically optimize the bus-based architectural topology [98,52,151]. Moreover, several design methodologies and design flow for customizing these architectures to adapt to traffic characteristics have further been studied [79,48,191]. However, many of these research aim at exploiting theories on the system-modeling level, making the implementations of the design flow difficult, sometimes unfeasible tasks.…”