A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms

Abstract

Reconfigurable platforms are a promising technology that offers an interesting trade-off between flexibility and performance, which many recent embedded system applications demand, especially in fields such as multimedia processing. These applications typically involve multiple ad-hoc tasks for hardware acceleration, which are usually represented using formalisms such as Data Flow Diagrams (DFDs), Data Flow Graphs (DFGs), Control and Data Flow Graphs (CDFGs) or Petri Nets. However, none of these models is able to capture at the same time the pipeline behavior between tasks (that therefore can coexist in order to minimize the application execution time), their communication patterns, and their data dependencies. This article proves that the knowledge of all this information can be effectively exploited to reduce the resource requirements and the timing performance of modern reconfigurable systems, where a set of hardware accelerators is used to support the computation. For this purpose, this article proposes a novel task representation model, named Temporal Constrained Data Flow Diagram (TCDFD), which includes all this information. This article also presents a mapping-scheduling algorithm that is able to take advantage of the new TCDFD model. It aims at minimizing the dynamic reconfiguration overhead while meeting the communication requirements among the tasks. Experimental results show that the presented approach achieves up to 75% of resources saving and up to 89% of reconfiguration overhead reduction with respect to other state-of-the-art techniques for reconfigurable platforms.

Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

“…In addition, it is assumed that task graphs are soft real-time, that decreasing makespan leads to increasing Quality of Service (QoS) [7], such as the H.264 video encoder [24].…”

“…This is a time-consuming process, especially in case of replicated tasks. This problem can be alleviated by applying a wellknown technique named task prefetch [15], [24], which consists in configuring the tasks before they are ready to be executed, in such a way that their configuration delay overlaps with the execution time of precedent tasks. This technique leads to achieve a better makespan which gives the opportunity of using more FT techniques.…”

“…The evaluated task graphs contain 10 tasks (to mimic H.264 and MP3 task graphs [24]), each of which is attributed with realistic characteristics. The computation times are selected between [10...500] ms [41].…”

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

“…Our second case study was a SPECfp benchmark (FP-5 from [CBP04]), characteristic for scientific and computation-intensive applications. Modern FPGAs, coupled with floating-point tools and IP, provide performance levels much higher than software-only solutions for such applications [Alt09].…”

“…Modern FPGAs, coupled with floating-point tools and IP, provide performance levels much higher than software-only solutions for such applications [Alt09]. In order to obtain the inputs needed for our experiments, we used the framework and traces provided for the first Championship Branch Prediction competition [CBP04]. The given instruction trace consists of 30 million instructions, obtained by profiling the program with representative inputs.…”