Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA

Abstract

Future applications for embedded systems demand chip multiprocessor designs to meet real-time deadlines. The large number of applications in these systems generates an exponential number of use-cases. The key design automation challenges are designing systems for these use-cases and fast exploration of software and hardware implementation alternatives with accurate performance evaluation of these use-cases. These challenges cannot be overcome by current design methodologies which are semiautomated, time consuming, and error prone.In this article, we present a design methodology to generate multiprocessor systems in a systematic and fully automated way for multiple use-cases. Techniques are presented to merge multiple use-cases into one hardware design to minimize cost and design time, making it well suited for fast design-space exploration (DSE) in MPSoC systems. Heuristics to partition use-cases are also presented such that each partition can fit in an FPGA, and all use-cases can be catered for.The proposed methodology is implemented into a tool for Xilinx FPGAs for evaluation. The tool is also made available online for the benefit of the research community and is used to carry out a DSE case study with multiple use-cases of real-life applications: H263 and JPEG decoders. The generation of the entire design takes about 100 ms, and the whole DSE was completed in 45 minutes, including FPGA mapping and synthesis. The heuristics used for use-case Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or direct commercial advantage and that copies show this notice on the first page or initial screen of a display along with the full citation. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept., ACM, Inc., 2 Penn Plaza, Suite 701, New York, NY 10121-0701 USA, fax +1 (212) 869-0481, or permissions@acm.org. partitioning reduce the design-exploration time elevenfold in a case study with mobile-phone applications.

Performance evaluation of concurrently executing parallel applications on multi-processor systems

“…We know that the token received in the FIFO is the processor time of previous processor, and according to Equation 1 the processor time can not decrease. Therefore ts f i f o (2) ≥ ts f i f o (1) . Hence time-stamps on a FIFO edge are guaranteed to be nondecreasing.…”

“…This technique has a very high overhead due to creation of complete state before execution of each sample. MAMPS [2] is a tool flow for mapping multi-media applications on FPGA. It evaluates the performance of applications by executing their models on the FPGA fabric, however we only forward the time-stamps of execution.…”

“…Let ts f i f o (1) and ts f i f o (2) be time-stamps of successive tokens sent from p 0 to p 1 . We know that the token received in the FIFO is the processor time of previous processor, and according to Equation 1 the processor time can not decrease.…”

“…To make matters worse, many applications are active simultaneously. Each combination of concurrently executing applications is defined as a use-case [2]. The number of these use-cases is exponential in the number of applications.…”

Predictable dynamic embedded data processing

“…It should also guarantee some bound on the time needed to execute a code segment (an actor of the dataflow graph) on a processor even when this processor is shared with actors from different applications. Several such predictable platforms have been proposed in recent years (e.g., MAMPS [28], CompSOC [12], PRET [13]). The precision-timed (PRET) platform focuses on the design of a processing element and memory controller that provide a predictable timing behavior.…”