Mapping concurrent applications on network-on-chip platforms

Bartic, T. Andrei; Desmet, D.; Mignolet, J.-Y.; Miller, Joel B.; Robert, Frédéric

doi:10.1109/sips.2005.1579856

Cited by 1 publication

(1 citation statement)

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“…The mapping and its optimization is a critical stage of any task graph based application running on a Networks-on-Chip (NoC) platform such as SpiNNaker. Several papers report that the mapping strategy can have a high impact on the overall system performance [1], [2], [3], [4].…”

Section: Introductionmentioning

confidence: 99%

Optimized task graph mapping on a many-core neuromorphic supercomputer

Sugiarto

Campos

Dahir

et al. 2017

2017 IEEE High Performance Extreme Computing Conference (HPEC)

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Abstract-This paper presents an approach for improving the overall performance of a general purpose application running as a task graph on a many-core neuromorphic supercomputer. Our task graph framework is based on graceful degradation and amelioration paradigms that strive to achieve high reliability and performance by incorporating fault tolerance and task spawning features. The optimization is applied on an instance of the task graph by performing a soft load balancing on the data traffic between nodes in the graph. We implemented the framework and its optimization on SpiNNaker, a manycore neuromorphic platform containing a million ARM9 processing cores. We evaluate our method using several static mapping examples, where some of them were generated using an evolutionary algorithm. The experiment demonstrates that a performance improvement of up to 8.2% can be achieved when implementing our algorithm on a fully-utilized SpiNNaker communication infrastructure.

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