System design, optimization and intelligent code generation for standard digital signal processors

Genin, D.; Moortel, Jan De; Desmet, D.; Velde, Erwin Van de

doi:10.1109/iscas.1989.100415

Cited by 20 publications

(5 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…But in a scheme developed in 1989 by Genin et al [155], a similar routine is executed before code generation. Targeting digital signal processors, their compiler first transforms the program into an internal signal-flow graph (ISFG), and then executes a routine-Genin et al called it a pattern matcher-which attempts to find several low-level operations in the ISFG that can be merged into single nodes.…”

Section: Running Peephole Optimization Before Instruction Selectionmentioning

confidence: 99%

Instruction Selection

Blindell

2016

View full text Add to dashboard Cite

Section: Running Peephole Optimization Before Instruction Selectionmentioning

confidence: 99%

Instruction Selection

Blindell

2016

View full text Add to dashboard Cite

“…On the one hand, he has to achieve a performance close to manual assembler code (as this would otherwise defeat the purpose of employing a special purpose processor) and on the other hand, he has to deal with a very specialized and arcane instruction set. Two major compilation/code generation approaches are currently in use: block oriented and direct code generation [4]. Examples of the block oriented systems are Grape [16], Gabriel [3] and its successor Ptolemy [11].…”

Section: Software Compilers For Single Programmable Dsp Processors (Pmentioning

confidence: 99%

“…While this approach ensures near optimal assembler code, it suffers from a lack of portability and depends heavily on the library size and quality. The reverse is true for the direct code generation, [4].…”

Section: Software Compilers For Single Programmable Dsp Processors (Pmentioning

confidence: 99%

Synthesis for real time systems: Solutions and challenges

Verbauwhede

Rabaey

1995

Journal of VLSI Signal Processing

View full text Add to dashboard Cite

Abstract.A real time system typically combines a variety of implementation technologies and hardware architectures. Deciding how to partition the system and selecting an architectural technology for the sub-systems is by no means a trivial task. These architectural decisions, which can have a major impact on the quality and performance of the final implementation, have to be made at the early stages in the design process, when the impact of the decisions is unclear and can only be quantified using some primitive measures.In this paper, we present our vision on how a next generation of design environment can aid the designer in this decision process. We first identify the problems of designing a heterogeneous real time system by walking through the design process of a complex speech recognition system. Based on this analysis, we propose a system design methodology build on top of current synthesis tools. Today, DSP synthesis tools are application and/or architecture specific, covering subparts of the application once the partitioning is made. To make them useful in the proposed methodology, a unified view on the underlying architecture assumptions is needed. Secondly, good decision making requires an "as-good-as-possible" estimation of the implications of the decision. Therefore, it is important that current manual estimation be enlarged by high level estimation and performance analysis tools.The HYPERSPACE environment, which is currently under development, therefore, consists of three complementary components: a set of architecture specific compilers, a set of estimation and performance analysis tools and an architecture selection and partitioning framework, steered by the designer.

show abstract

“…One way to guarantee both properties is to impose certain restrictions so that the considered subset of DPNs are deterministic and have decidable boundedness or liveness problems. Synchronous data-flow (SDF) networks [4,6,9,21,[25][26][27] and cyclo-static data-flow networks [7,12] are such restricted nets, which have become very successful, in particular, for the synthesis of signal processing systems [1,6,13,14,22,23,29,31]. They are a special kind of DPNs where in each firing step, the process node always consumes the same number of data values from the input streams and produces the same number of data values for the output streams.…”

Section: Introductionmentioning

confidence: 99%

Out-Of-order execution of synchronous data-flow networks

Baudisch

Brandt

Schneider

2012

2012 International Conference on Embedded Computer Systems (SAMOS)

View full text Add to dashboard Cite

Data flow process networks (DPNs) have been introduced as a convenient model of computation for distributed and asynchronous systems since each process node can work independently of the other nodes, i. e. without the need of a global coordination. Synchronous and cyclo-static data flow process networks even allow to derive at compile-time efficient static schedules that allow one to run these systems with an efficient use of available resources, e. g. in embedded systems. Single process nodes of DPNs are stream-based computing devices that transform input streams to uniquely defined corresponding output streams such that single values of the output streams are computed as soon as sufficient input values are available. In this sense, they are related to the execution of an instruction stream by a conventional microprocessor. In this paper, we show how out-of-order execution that has been introduced for the efficient use of multiple functional units in microprocessors can also be used for the implementation of DPNs on multiprocessors. This way, the implementation of DPNs on multiprocessors allows one to optimize the throughput of single process nodes, and as shown by our experiments, also of the entire DPN.

show abstract

System design, optimization and intelligent code generation for standard digital signal processors

Cited by 20 publications

References 5 publications

Instruction Selection

Instruction Selection

Synthesis for real time systems: Solutions and challenges

Out-Of-order execution of synchronous data-flow networks

Contact Info

Product

Resources

About