Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays

Sutter, Bjorn De; Coene, Paul; Aa, Tom Vander; Mei, Bingfeng

doi:10.1145/1375657.1375678

Cited by 23 publications

(30 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Using local register files connected to processing elements: Reduces the overhead of accessing centralized general-purpose register files. This solution is also used in other approaches [8,9,16,20,31,32]. 5.…”

Section: Eliminating the Need For Intermediate Dfg Generationmentioning

confidence: 99%

See 1 more Smart Citation

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

Ferreira

Denver

Pereira

et al. 2015

J Sign Process Syst

View full text Add to dashboard Cite

In the past years, many works have demonstrated the applicability of Coarse-Grained Reconfigurable Array (CGRA) accelerators to optimize loops by using software pipelining approaches. They are proven to be effective in reducing the total execution time of multimedia and signal processing applications. However, the run-time reconfigurability of CGRAs is hampered overheads introduced by the needed translation and mapping steps. In this work, we present a novel run-time translation technique for the modulo scheduling approach that can convert binary code onthe-fly to run on a CGRA. We propose a greedy approach, since the modulo scheduling for CGRA is an NP-complete problem. In addition to read-after-write dependencies, the dynamic modulo scheduling faces new challenges, such as register insertion to solve recurrence dependences and to balance the pipelining paths. Our results demonstrate that the greedy run-time algorithm can reach a near-optimal ILP rate, better than an off-line compiler approach for a 16-issue VLIW processor. The proposed mechanism ensures software compatibility as it supports different source ISAs. As proof of concept of scaling, a change in the memory bandwidth has been evaluated. In this analysis it is demonstrated R. Ferreira ( ) · W. Denver that when changing from one memory access per cycle to two memory accesses per cycle, the modulo scheduling algorithm is able to exploit this increase in memory bandwidth and enhance performance accordingly. Additionally, to measure area and performance, the proposed CGRA was prototyped on an FPGA. The area comparisons show that a crossbar CGRA (with 16 processing elements and including an 4-issue VLIW host processor) is only 1.11 × bigger than a standalone 8-issue VLIW softcore processor.

show abstract

Section: Eliminating the Need For Intermediate Dfg Generationmentioning

confidence: 99%

“…To the best of our knowledge, this is the first work to propose a BT run-time modulo scheduling algorithm for CGRAs. The proposed BT MS algorithm reduces mapping time by proposing alternatives to many of the complex solutions presented in previous modulo scheduling algorithms [8,9,11,14,27,29,32]:…”

Section: Introductionmentioning

confidence: 99%

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

Ferreira

Denver

Pereira

et al. 2015

J Sign Process Syst

View full text Add to dashboard Cite

show abstract

“…This follows from the fact that loads and stores might be reordered by the compiler, and by the fact that software-pipelined schedules are generated, in which code corresponding to different iterations in the source code is executed simultaneously. In our current version, the compiler [11,21] schedules the code completely bank-unaware. 1 As such, even if the strides might look alright in the source code, there might still be many conflicting simultaneous accesses in the scheduled code.…”

Section: Memory Access Patterns and Interleavingmentioning

confidence: 99%

“…Furthermore, our prototype compiler does not yet apply complex loop transformations such as loop unrolling to increase the amount of available ILP. For more information on the compiler, we refer to [11,21]. Alternative compiler code generation techniques for architectures like ours exist [12,23,26].…”

Section: The Wireless Standardsmentioning

confidence: 99%

“…While reusing code is beneficial for limiting the overall code footprint, the reuse of a kernel prohibits its specialization or optimization for any single execution context. The lack of regularity results from the code generation techniques used in high-ILP compilers [11,12,21,23,26]. These compilers usually generate software-pipelined code in which loads and stores from many iterations are mixed in irregular ways that are most often not easily predictable at compile time.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors

Sutter

Allam

Raghavan

et al. 2009

J Sign Process Syst

Self Cite

View full text Add to dashboard Cite

This paper presents a memory organization for SDR inner modem baseband processors that focus on exploiting ILP. This memory organization uses power-efficient, single-ported, interleaved scratch-pad memory banks to provide enough bandwidth to a high-ILP processors. A system of queues in the memory interface is used to resolve bank conflicts among the single-ported banks, and to spread long bursts of conflicting accesses to the same bank over time. Bank address rotation is used to spread long bursts of conflicting accesses over multiple banks. All proposed techniques have been implemented in hardware, and are evaluated for a number of different wireless communication standards. For the 11a|n benchmarks, the overhead of stall cycles resulting from unresolved bank conflicts can be reduced to below 2% with the proposed organization. For 3GPP-LTE, the most demanding wireless standard we evaluated, the overhead is reduced to less than 0.13%. This is achieved with little energy and area overhead, and without any bank-aware compiler support.

show abstract

Coarse-Grained Reconfigurable Array Architectures

Sutter

Raghavan

Lambrechts

2010

Handbook of Signal Processing Systems

Self Cite

View full text Add to dashboard Cite

Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.

show abstract

Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays

Cited by 23 publications

References 24 publications

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors

Coarse-Grained Reconfigurable Array Architectures

Contact Info

Product

Resources

About