A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

Abstract

In the past years, many works have demonstrated the applicability of Coarse-Grained Reconfigurable Array (CGRA) accelerators to optimize loops by using software pipelining approaches. They are proven to be effective in reducing the total execution time of multimedia and signal processing applications. However, the run-time reconfigurability of CGRAs is hampered overheads introduced by the needed translation and mapping steps. In this work, we present a novel run-time translation technique for the modulo scheduling approach that can convert binary code onthe-fly to run on a CGRA. We propose a greedy approach, since the modulo scheduling for CGRA is an NP-complete problem. In addition to read-after-write dependencies, the dynamic modulo scheduling faces new challenges, such as register insertion to solve recurrence dependences and to balance the pipelining paths. Our results demonstrate that the greedy run-time algorithm can reach a near-optimal ILP rate, better than an off-line compiler approach for a 16-issue VLIW processor. The proposed mechanism ensures software compatibility as it supports different source ISAs. As proof of concept of scaling, a change in the memory bandwidth has been evaluated. In this analysis it is demonstrated R. Ferreira ( ) · W. Denver that when changing from one memory access per cycle to two memory accesses per cycle, the modulo scheduling algorithm is able to exploit this increase in memory bandwidth and enhance performance accordingly. Additionally, to measure area and performance, the proposed CGRA was prototyped on an FPGA. The area comparisons show that a crossbar CGRA (with 16 processing elements and including an 4-issue VLIW host processor) is only 1.11 × bigger than a standalone 8-issue VLIW softcore processor.

Dynamic Translation Optimization Method Based on Static Pre-Translation

“…This is the basic for dynamic translator to use the code translated by static translation. To reduce the overhead of the whole translation process, to increase the efficiency of the whole runtime better and to make full use of the advantages of static binary translation, the cost of dynamic translation process should be analyzed firstly [23].…”

Design exploration of machine learning data-flows onto heterogeneous reconfigurable hardware

“…The placement and routing of graphs on rectangular grids is an NP-Complete problem that has been studied for a long time and has also been approached in different manners, for example we have greedy algorithms (Ferreira et al, 2005), integer linear programming (Walker and Anderson, 2019), SAT-solvers (Donovick et al, 2019), reinforcement learning (Liu et al, 2018), graph traversal approaches (Ferreira et al, 2013b;Vieira et al, 2021), run-time approaches (Ferreira et al, 2014(Ferreira et al, , 2016, genetic algorithms (Silva et al, 2006) and simulated annealing based algorithms like the one used by VPR (Luu et al, 2011), which happens to be the algorithm to which the results of this work were compared to. The placement is particularly difficult because there are many different constraints that have to be taken into account.…”