Coarse-Grained Reconfigurable Array Architectures

Abstract

Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.

Physics engine on reconfigurable processor — Low power optimized solution empowering next-generation graphics on embedded platforms

“…Also there can be cases where each group will have very less number of pairs, down to even one. Executing very less number of iterations in CGA is not optimal [5]. We present a new method of rescheduling and splitting the collision pairs which utilizes the CGA efficiently.…”

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“…not DRRA) and Silicon Hive efforts [15]. A fairly recent comprehensive review of CGRAs by Sutter et al summarizes the activities in this area [16]. In such systems, the loop indices are computed and sent to the FUs in a centralized fashion by the VLIW machine.…”

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