Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric

Farahini, Nasim; Hemani, Ahmed; Sohofi, Hassan; Jafri, Syed M. A. H.; Tajammul, Muhammad Adeel; Paul, Kolin

doi:10.1016/j.micpro.2014.05.009

Cited by 15 publications

(4 citation statements)

References 27 publications

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“…An AGU can be programmed to generate the address sequence used to access data from the memory port, during the execution of a program loop in the DE. The AGU scheme is similar to the one described in [41], in the sense that both schemes use parallel and distributed AGUs. The AGUs in this work support two levels of nested loops.…”

Section: Address Generationmentioning

confidence: 99%

Coarse-Grained Reconfigurable Computing with the Versat Architecture

et al. 2021

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Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architectures. Unlike most of the existing approaches, which mainly use pre-compiled configurations, a Versat program can generate and apply myriads of on-the-fly configurations. Partial reconfiguration plays a central role in this approach, as it speeds up the generation of incrementally different configurations. The reconfigurable array has a complete graph topology, which yields unprecedented programmability, including assembly programming. Besides being useful for optimising programs, assembly programming is invaluable for working around post-silicon hardware, software, or compiler issues. Results on core area, frequency, power, and performance running different codes are presented and compared to other implementations.

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Section: Address Generationmentioning

confidence: 99%

Coarse-Grained Reconfigurable Computing with the Versat Architecture

et al. 2021

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“…However, the access pattern of a real application may not follow the same pattern as the refreshes. To adapt the refresh scheme to arbitrary access patterns, RTT implements an Address Generation Unit (AGU) that is similar to the proposal in prior work [21]. AGUs are commonly used in Digital Signal Processors (DSPs) to efficiently generate the memory addresses to feed to the functional units [21,70,71,107,112,113].…”

Section: Refresh Triggered Transfermentioning

confidence: 99%

Refresh Triggered Computation

Jafri

Hassan

Hemani

et al. 2020

ACM Trans. Archit. Code Optim.

Self Cite

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To employ a Convolutional Neural Network (CNN) in an energy-constrained embedded system, it is critical for the CNN implementation to be highly energy efficient. Many recent studies propose CNN accelerator architectures with custom computation units that try to improve the energy efficiency and performance of CNNs by minimizing data transfers from DRAM-based main memory. However, in these architectures, DRAM is still responsible for half of the overall energy consumption of the system, on average. A key factor of the high energy consumption of DRAM is the refresh overhead , which is estimated to consume 40% of the total DRAM energy. In this article, we propose a new mechanism, Refresh Triggered Computation (RTC) , that exploits the memory access patterns of CNN applications to reduce the number of refresh operations . RTC uses two major techniques to mitigate the refresh overhead. First, Refresh Triggered Transfer (RTT) is based on our new observation that a CNN application accesses a large portion of the DRAM in a predictable and recurring manner. Thus, the read/write accesses of the application inherently refresh the DRAM, and therefore a significant fraction of refresh operations can be skipped. Second, Partial Array Auto-Refresh (PAAR) eliminates the refresh operations to DRAM regions that do not store any data. We propose three RTC designs (min-RTC, mid-RTC, and full-RTC), each of which requires a different level of aggressiveness in terms of customization to the DRAM subsystem. All of our designs have small overhead. Even the most aggressive RTC design (i.e., full-RTC) imposes an area overhead of only 0.18% in a 16 Gb DRAM chip and can have less overhead for denser chips. Our experimental evaluation on six well-known CNNs shows that RTC reduces average DRAM energy consumption by 24.4% and 61.3% for the least aggressive and the most aggressive RTC implementations, respectively. Besides CNNs, we also evaluate our RTC mechanism on three workloads from other domains. We show that RTC saves 31.9% and 16.9% DRAM energy for Face Recognition and Bayesian Confidence Propagation Neural Network (BCPNN) , respectively. We believe RTC can be applied to other applications whose memory access patterns remain predictable for a sufficiently long time.

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“…However, the access pattern of a real application may not follow the same pattern as the refreshes. To adapt the refresh scheme to arbitrary access patterns, RTT implements an Address Generation Unit (AGU) that is similar to the proposal in prior work [16]. We implement AGU as a part of the DRAM circuitry and it can be configured to generate address patterns based on arbitrary affine function.…”

Section: Refresh Triggered Transfermentioning

confidence: 99%

Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators

Jafri¹,

Hassan²,

Hemani³

et al. 2019

Preprint

Self Cite

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To employ a Convolutional Neural Network (CNN) in an energy-constrained embedded system, it is critical for the CNN implementation to be highly energy efficient. Recently, many studies proposed CNN accelerator architectures with custom computation units that try to improve energy-efficiency and performance of CNN by minimizing data transfers from DRAMbased main memory. However, in these architectures, DRAM still contributes half of the overall energy consumption of the system, on average. A key factor of the high energy consumption of DRAM is the refresh overhead, which is estimated to consume 40% of the total DRAM energy.In this paper, we propose a new mechanism, Refresh Triggered Computation (RTC), that exploits the memory access patterns of CNN applications to reduce the number of refresh operations. RTC mainly uses two techniques to mitigate the refresh overhead. First, Refresh Triggered Transfer (RTT) is based on our new observation that a CNN application accesses a large portion of the DRAM in a predictable and recurring manner. Thus, the read/write accesses inherently refresh the DRAM, and therefore a significant fraction of refresh operations can be skipped. Second, Partial Array Auto-Refresh (PAAR) eliminates the refresh operations to DRAM regions that do not store any data.We propose three RTC designs, each of which requires a different level of aggressiveness in terms of customization to the DRAM subsystem. All of our designs have small overhead. Even the most aggressive design of RTC imposes an area overhead of only 0.18% in a 2Gb DRAM chip and can have less overhead for denser chips. Our experimental evaluation on three well-known CNNs (i.e., AlexNet, LeNet, and GoogleNet) show that RTC can reduce the DRAM refresh energy from 25% to 96%, for the least aggressive and the most aggressive designs, respectively. Although we mainly use CNNs in our evaluations, we believe RTC can be applied to a wide range of applications, whose memory access patterns remain predictable for sufficiently long time.

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Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric

Cited by 15 publications

References 27 publications

Coarse-Grained Reconfigurable Computing with the Versat Architecture

Coarse-Grained Reconfigurable Computing with the Versat Architecture

Refresh Triggered Computation

Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators

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