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The flatbandhhreshold voltages (VJV,) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO2 at poly-Si deposition temperatures is identified as the root cause for the poor VJV, control. No improvement in V, control is obtained by engineering physically closed Si3N4 barrier layers on Hf02. It is furthermore shown for the first time that even when the gate is fully silicided (FUSI) large VnJV, shifts are observed with HfO,. Reduced pFET shifts are observed when Hf-silicates with low Hf content are used and further improvements are observed by using AI203 cap layers on silicates.

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