Training and recognition with neural networks generally require high throughput, high energy efficiency, and scalable circuits to enable artificial intelligence tasks to be operated at the edge, i.e., in battery-powered portable devices and other limited-energy environments. In this scenario, scalable resistive memories have been proposed as artificial synapses thanks to their scalability, reconfigurability, and high-energy efficiency, and thanks to the ability to perform analog computation by physical laws in hardware. In this work, we study the material, device, and architecture aspects of resistive switching memory (RRAM) devices for implementing a 2-layer neural network for pattern recognition. First, various RRAM processes are screened in view of the device window, analog storage, and reliability. Then, synaptic weights are stored with 5-level precision in a 4 kbit array of RRAM devices to classify the Modified National Institute of Standards and Technology (MNIST) dataset. Finally, classification performance of a 2-layer neural network is tested before and after an annealing experiment by using experimental values of conductance stored into the array, and a simulation-based analysis of inference accuracy for arrays of increasing size is presented. Our work supports material-based development of RRAM synapses for novel neural networks with high accuracy and low-power consumption.

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A thorough study of the admittance of TiN/Ti/HfO 2 /W bipolar resistive memories [resistance random access memory (RRAM)] was carried out under different bias conditions and in a wide range of ac signal frequencies. We demonstrate that a continuum of intermediate states can be obtained by applying appropriate dc bias waveforms. Cumulative writing and erasing admittance cycles were performed by applying triangular voltage waveform of increasing amplitude. The influence of the initial conditions on the variation of the real (conductance) and imaginary (susceptance) components of the admittance is described. An accurate control of the memory state is achieved both in terms of the conductance and the susceptance by means of an adequate selection of the voltage values previously applied. A method to obtain three-dimensional voltage-conductance-susceptance state-plots is described in detail. Memory maps of admittance parameters as a function of the programming voltage are made by sensing the memory state at 0 V, without static power consumption. The multilevel nature of RRAM devices and their suitability for neuromorphic computation are demonstrated.

A crucial step in order to achieve fast and low-energy switching operations in resistive random access memory (RRAM) memories is the reduction of the programming pulse width. In this study, the incremental step pulse with verify algorithm (ISPVA) was implemented by using different pulse widths between 10 μ s and 50 ns and assessed on Al-doped HfO 2 4 kbit RRAM memory arrays. The switching stability was assessed by means of an endurance test of 1k cycles. Both conductive levels and voltages needed for switching showed a remarkable good behavior along 1k reset/set cycles regardless the programming pulse width implemented. Nevertheless, the distributions of voltages as well as the amount of energy required to carry out the switching operations were definitely affected by the value of the pulse width. In addition, the data retention was evaluated after the endurance analysis by annealing the RRAM devices at 150 °C along 100 h. Just an almost negligible increase on the rate of degradation of about 1 μ A at the end of the 100 h of annealing was reported between those samples programmed by employing a pulse width of 10 μ s and those employing 50 ns. Finally, an endurance performance of 200k cycles without any degradation was achieved on 128 RRAM devices by using programming pulses of 100 ns width.

A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two multilevel programming algorithms to minimize resistance variations in a 4-kbit array of HfO2 RRAM. We show that gate-based algorithms have the highest reliability. The optimized scheme is used to implement a neural network with 9-level weights, achieving 91.5% (vs. software 93.27%) in MNIST recognition.

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Due to the high number of reachable conductance levels in resistive switching devices, they are good candidates to implement artificial synaptic devices. In this work, we have studied the control of the intermediate conductance levels in HfO 2-based MIM capacitors using current pulses. The set transition can be controlled in a linear way using this kind of signal. The potentiation characteristic is not affected by the pulse length due to the filament formation takes place in very short times. This behavior does not allow using identical pulses to obtain the potentiation characteristic. The transient response of the devices when applying current pulses showed the filament formation is characterized by a peak in the voltage transient signal. No depression characteristic can be obtained using current signals due to the abrupt reset transition. However, the depression characteristic can be obtained using voltage pulses, so combining both signals should allow control the synaptic weight in an appropriate way.

RRAM devices are promising candidates to implement artificial synaptic devices for their use in neuromorphic systems, due to their high number or reachable conductance levels.The capacitors used in this work (TiN/Ti/ HfO2/W) show resistive switching behavior and reachable intermediate conductance states. We can control the conductance states by applying voltage pulses to the top electrode. Different approaches to control the synaptic weight have been studied: applying pulses with different amplitudes changes the synaptic weight variation in an exponential way and applying pulses with different lengths changes the synaptic weight in a linear weight. We can control the conductance values when applying depression pulses, but the potentiation characteristic is not linear, as for other synaptic devices, as PRAMs. Applying other voltage signals to the structure, as voltage ramps, can improve the potentiation characteristic.