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An inverter-based track-and-hold circuit that merges the functions of buffering and sampling is proposed, simultaneously improving linearity, bandwidth and power efficiency when compared to stateof-the-art designs. The circuit operation and its governing equations are presented, and simulation results of an 80 GS/s, 5.5 ENOB timeinterleaved prototype consuming 25 mW from a 0.7 V supply demonstrate the advantages of the proposed topology using a predictive 7 nm FinFET CMOS technology.

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A novel resistorless bipolar junction transistor (BJT) bias and curvature compensation circuit for ultra-low power CMOS bandgap voltage references (BGR) is introduced. It works in the nano-ampere current consumption range and under 1 V of power supply. The analytical behavior of the circuit is described, and simulation results for a 0.18 µm CMOS standard process are analysed. A junction voltage of 550 mV at room temperature is obtained (at an emitter current of 3.5 nA), presenting an almost linear temperature dependence, while the power consumption of the whole circuit is 3.4 nW under a 0.8 V power supply at 27 o C. The estimated silicon area is 0.00135 mm 2 .

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In this work a new resistorless sub-bandgap voltage reference topology is presented. It is a self-biased and small area circuit that works in the nano-ampere consumption range, and under 1 V of power supply. The behavior of the circuit is analitically described, a design methodology is proposed and simulation results are presented for a standard 0.18 µm CMOS process. A reference voltage of 463 mV is demonstrated, with a temperature coefficient of 8 ppm/ o C for the 0 to 125 • C range, while the power consumption of the whole circuit is 8.25 nW under a 0.75 V power supply at 27 o C. The estimated silicon area is 0.0043 mm 2 .

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