80 GS/s 5.5 ENOB time‐interleaved inverter‐based CMOS track‐and‐hold

Mattia, Oscar E.; Murmann, Boris

doi:10.1049/el.2019.4104

Cited by 4 publications

(5 citation statements)

References 7 publications

(11 reference statements)

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“…These eight buffers must support an input common-mode around half of the supply voltage to accommodate the output common-mode of the previous stage. Suitable solutions are the ones used in [13,14], which are gm-gm inverter-based topologies. These topologies are very simple to design while having good speed and linearity.…”

Section: Circuit Descriptionmentioning

confidence: 99%

A Track-and-Hold Circuit with Tunable Non-Linearity and a Calibration Loop for PAM-8 SerDes Receivers

Pasquo

Monaco²,

Ghittori³

et al. 2022

Electronics

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In this brief, we propose a 60 GS/s high-linearity two-stage 8 × 8 time-interleaved track-and-hold circuit where it is possible to tune the static non-linearities of the second-stage buffer by applying a proper bias voltage. This allows us to maximize the static linearity of the buffer or introduce effects that counterbalance the non-linearities of other blocks of the analog front-end. To validate the proposed circuit, a prototype in TSMC 5 nm technology is designed and a linearity calibration loop is proposed for a Pulse Amplitude Modulation SerDes receiver. For the analog buffer, circuit-level simulations are performed in Cadence Virtuoso, while the calibration loop is simulated in MATLAB. The optimal bias voltage value can be found by modeling the track-and-hold linearity using a Taylor series and implementing the linearity calibration loop in MATLAB. By applying this result to the circuit-level simulation, we obtain a total harmonic distortion of over 50 dB, which matches with the maximum value achievable across the complete bias voltage control range. Lastly, the linearity of the system is also verified using a PAM-8 pseudorandom stream signal.

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Section: Circuit Descriptionmentioning

confidence: 99%

A Track-and-Hold Circuit with Tunable Non-Linearity and a Calibration Loop for PAM-8 SerDes Receivers

Pasquo

Monaco²,

Ghittori³

et al. 2022

Electronics

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“…In [6] an alternative solution is proposed that shows higher linearity compared to the one discussed in section II.A, while delivering a large bandwidth.…”

Section: B Inverter-based Sampling Buffermentioning

confidence: 99%

“…To overcome the limitations of this approach, new ideas were introduced in [5] and [6]. Instead of using a buffer followed by a series switch, a sampling buffer is implemented.…”

Section: Introductionmentioning

confidence: 99%

“…This allows sampling of the signal inside the buffer itself and to remove the resistance introduced by the series switch. The solution proposed in [5] shows limited linearity performance reducing the dynamic range (SFDR) while the one proposed in [6] shows an input capacitance that scales unfavorably with the increasing of the interleaving factor. For this reason, a sampling buffer topology is proposed in this paper which addresses these problems.…”

Section: Introductionmentioning

confidence: 99%

“…This paper is organized as follows. The two sampling buffers [5] and [6] and a simple buffer topology that uses the standard approach are discussed in Section II. In Section III, a circuit is proposed, and its linearity behavior is studied.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADC

Pasquo

Nani

Monaco

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a Track and Hold sampling buffer topology, which allows sampling the signal inside the buffer itself while achieving very high linearity. The circuit operations and its large-signal behavior are analyzed and the key design strategies to maximize linearity are discussed. Then, a / , . SFDR, 8 ways interleaved simulated prototype in TSMC technology, consuming . from a . supply, is compared to the state-ofthe-art sampling buffers, showing linearity improvement.

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