0.9 V, 5 nW, 9 ppm/&lt;sup&gt;o&lt;/sup&gt;C resistorless sub-bandgap voltage reference in 0.18&amp;#x03BC;m CMOS

Mattia, Oscar E.; Klimach, Hamilton; Bampi, Sérgio

doi:10.1109/lascas.2014.6820273

Cited by 8 publications

(4 citation statements)

References 14 publications

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“…1. In this circuit, the BJT junction voltage is counterbalanced by the gate-source voltage of two stacked nMOS transistors M1 and M2 [3]. The resulting gate-source voltage defines the BJT emitter current, through a feedback path that uses a current mirror with gain K 1 .…”

Section: Circuit Descriptionmentioning

confidence: 99%

“…This non-linearity is the main contributor to the curvature over temperature usually seen in such circuits, and it directly impacts the temperature coefficient (TC) of the reference voltage. If a TC under 10 ppm/ • C is to be achieved, resistorless BGRs must either operate under a limited temperature range [3] or implement a curvature compensation technique [4].…”

Section: Introductionmentioning

confidence: 99%

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0.7 V supply, 8 nW, 8 ppm/°C resistorless sub-bandgap voltage reference

Mattia

Klimach

Bampi

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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In this work a new resistorless sub-bandgap voltage reference topology is presented. It is a self-biased and small area circuit that works in the nano-ampere consumption range, and under 1 V of power supply. The behavior of the circuit is analitically described, a design methodology is proposed and simulation results are presented for a standard 0.18 µm CMOS process. A reference voltage of 463 mV is demonstrated, with a temperature coefficient of 8 ppm/ o C for the 0 to 125 • C range, while the power consumption of the whole circuit is 8.25 nW under a 0.75 V power supply at 27 o C. The estimated silicon area is 0.0043 mm 2 .

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Section: Circuit Descriptionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

0.7 V supply, 8 nW, 8 ppm/°C resistorless sub-bandgap voltage reference

Mattia

Klimach

Bampi

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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“…Since we choose i f 1 = 3, ID1 = 3S1ISQ, and this current is mirrored to bias the rest of the circuit through pMOS transistors M5-M7, M12 and M17. The reference voltage VREF , at the gate of M13, is the sum of a CTAT term given by (6) and twice the PTAT term given by (9), hence:…”

Section: Voltage Reference Circuitmentioning

confidence: 99%

“…Still, even in modern CMOS approaches they consume high power [8]. References that do not implement curvature compensation usually do not achieve low temperature coefficients [9] or operate under a limited temperature range [6]. Switched capacitors can also be used to reduce fabrication variability [4], but the curvature effect is still present.…”

Section: Introductionmentioning

confidence: 99%

2.3 ppm/°c 40 nW MOSFET-only voltage reference

Mattia

Klimach

Bampi

2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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A MOSFET-only sub-bandgap voltage reference at less than 50 nW and with very low temperature coefficient is introduced. It consists of a threshold voltage extractor circuit and a proportional to absolute temperature voltage generator, using no resistors. The behavior of the circuit is analytically described, a design methodology is proposed and simulation results for a 0.13µm CMOS process are presented. It allows a reference voltage below the bandgap, 625 mV in this design example, achieving a temperature coefficient of 2.3 ppm/ • C for the -40 to 125 • C temperature range. The circuit consumes 40 nW at 27 • C and under 1.2 V supply, being the implemented silicon area 0.0099 mm 2 .

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