In this paper and using the charge pumping method, it is shown that in state-of-the-art fully processed MOSFET's the Si-SiO2 interface traps have the same properties as those of the Pb0 center. The question as to whether these defects are Pb0 centers is discussed. Devices using HfO2 as gate dielectric are also studied. In spite of some differences, it is found that the traps at the Si-SiO2 interface in these devices have the same properties as those in state-of-the-art fully processed MOSFET's. These differences are discussed. Finally, a method for extracting the interface trap density from the slope of the charge pumping curves is proposed and applied to the two kinds of devices studied.
The present research letter is dedicated to a detailed analysis of a double-gate tunnel field-effect transistor (DG-TFET). The DG-TFET provides improved on-current (I ON) than a conventional TFET via bandto-band (B2B) tunneling. However, DG-TFET is disadvantageous for low-power applications because of increased off-current (I OFF) due to the large ambipolar current (I amb). In this research work, a Si/GaAs/ GaAs heterostructure DG-TFET is considered as research base for investigation of device performance. The electrical parameters of the DG-TFET device have been improved in comparison to the homostructure. The transfer (I-V) characteristics, capacitance-voltage (C-V) characteristic of homo structure Si/ Si/Si and hetero structure Si/GaAs/GaAs, DG-TFET both structures is analysed comparatively. The C-V characteristics of DG-TFET have obtained using operating frequency of 1 MHz. The ambipolar current Iamb is suppressed by 5 × 10 8 order of magnitude in proposed Si/GaAs/GaAs hetero DG-TFET as compared to Si/Si/Si homo DG-TFET up to the applied drain voltage very low equal to VDS = 0.5 V without affecting on-state performance. The simulation result shows a very good I ON /I OFF ratio (10 13) and low subthreshold slope, SS (~36.52 mV/dec). The various electrical characteristics of homo and hetero DG-TFET such as on-current (I ON), off-current (I OFF), time delay (ι d), transconductance (g m) , and power delay product (PDP) have been improve in Si/GaAs/GaAs heterostructure DG-TFET and compared with Si/Si/ Si homo DG-TFET. The advantageous results obtained for the proposed design show its usability in the field of digital and analog applications.
The Equilibrium Voltage Step (EVS) technique has been used for extraction of depth and energy concentration profile of traps situated in the oxide of a lightly stressed metal-oxidesemiconductor (MOS) structure. This has been achieved up to the very near Si-SiO 2 interface. The results are discussed and compared with those obtained using charge pumping (CP) technique. A good agreement is achieved between the trap densities extracted using the two methods even though differences in the shape of the profiles can be observed. The results also very well agree with those published previously using current deep level transient spectroscopy (C-DLTS).
A charge pumping (CP) technique has been proposed more than two decades ago to extract the Si(100)-SiO 2 interface trap time constant distribution (ITTCD) that exists at this interface. To that aim, several Elliot curves (1) needed to be recorded at a frequency, f 0 , of the order of f 0 =10 4 Hz and for a set of selected gate voltage swing, Vsw, values. The charge recombining during one period of the gate signal, Qcp 0 =Icp 0 /f 0 was extracted from the maximum CP current measured, Icp 0 , at f 0 , supposed to result from recombination due to identical electron and hole free carrier concentrations at the interface. From Qcp 0 , the recombined charge was finally measured as function of frequency, f, yielding a set of Qcp 0 (f) curves, one for each Vsw value. Assuming, as done primarily, that carrier capture resulted from tunneling from the interface to the traps in the near oxide, the set of Qcp 0 (f) curves provided a single trap "depth" concentration profile. The same kind of profile was recorded from n-and p-channel MOSFETs of different technologies (2, 3). As Pb0 centers are known to be the amphoteric defects that characterize the Si(100)-SiO 2 interface, even after forming annealing in conventional MOSFETs with thermally grown oxides, and as these centers are located at the interface, the trap time constant distribution was re-interpreted. Then, in order to evidence the way the Pb0 centers occupy the interface, the experimental conditions primarily used to extract the profiles are modified. These results are discussed with regard to previous work in that field (4, 5) and to recent results obtained by T. Tsuchiya and co-workers on submicron devices (6, 7).
A tunnel field effect transistor (TFET) is a gate-controlled, band to band tunneling (BTBT) transport of charge carriers having low subthreshold swing(SS < 60 mV/decade|T = 300K). With TFETs, low-ION is a built-in problem which limits its adaptability to high-speed, low-power uses. To overcome this limitation, a conventional double-gate TFET was constructed having ferroelectric (BaTiO3)/HfO2 gate materials and a source/channel region with Si1-xGex/Si semiconductor channel composition. This design enhances the ION and lowers the subthreshold swing (SS). Analysis using the Silvaco simulator shows improvement in ION current approximately 103 times better than that of conventional DGTFET, without affecting IOFF. Ultimately, a change in ION from 10-8 A/µm to 10-5 A/µ was measured for VDS~0.5 V at room temperature. IOFF of ~10-20 A/µm was measured. In addition to this, a first time genetic algorithm has been used for the optimization of ferroelectric TFET (Fe-TFET) device design parameters like a subthreshold swing (SS), ambipolar current (Iamb), and ION by using device design parameters, doping (NS, ND), dielectric (εOX), and work function (WF). This research shows that Fe-Tunnel can play a leading role for super-low-power applications in advanced VLSI circuits and systems.
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