Advanced Analysis of Silicon Insulator Interface Traps in MOSFET's with SiO2 and HfO2 as Gate Dielectrics

Abstract

In this paper and using the charge pumping method, it is shown that in state-of-the-art fully processed MOSFET's the Si-SiO2 interface traps have the same properties as those of the Pb0 center. The question as to whether these defects are Pb0 centers is discussed. Devices using HfO2 as gate dielectric are also studied. In spite of some differences, it is found that the traps at the Si-SiO2 interface in these devices have the same properties as those in state-of-the-art fully processed MOSFET's. These differences are discussed. Finally, a method for extracting the interface trap density from the slope of the charge pumping curves is proposed and applied to the two kinds of devices studied.

Detailed Analysis of Si-SiO2 Interface Traps in State-of-the-Art MOSFETs Using Charge Pumping

“…As a result, CP curves recorded from conventional and fresh MOSFET such as those studied here, are supposed to mainly probe Si-SiO 2 interface traps so that D it can be extracted from CP curves maximum after accounting for carrier re-emission [29,36]. The above results demonstrate that D it also straightforwardly enters the slope of the CP curves in a region where capture still governs Q cp magnitude as will be shown.…”

“…In our studies dealing with Si-SiO 2 interface trap properties in MOSFETs with thick SiO 2 using CP, two different n-channel devices were employed [11,[27][28][29][30][31][32][33]. Those used in this study have an oxide thickness, d ox = 27 nm, a doping concentration N a ≈ 2x10 16 cm -3 and an interface trap density, D it ≈ 4-6x10 10 eV -1 cm -2 .…”

“…In spite of a tenfold difference in their D it values (D it ≈ 2-3x10 9 eV -1 cm -2 vs. D it ≈ 4-6x10 10 eV -1 cm -2 ), the two device types always provided identical results in terms of trap properties [10]. They have therefore been regarded as good examples of fresh and fully processed MOSFETs with thick oxides, well suited for Si-SiO 2 interface CP studies [10,[27][28][29][30][31][32][33].…”

“…The two interface trap types seem to belong to the Si-SiO 2 interface in such fresh and fully processed MOSFETs and could therefore be observed in such devices provided that small enough V sw are used [28,29,32]. When the TCD is supposed to result from carrier tunneling through the Si-SiO 2 barrier [27,32], the tunneling attenuation length for electrons and for holes, λ e and λ h , were taken equal.…”

“…The simulation of this first kind of curves has been published primarily in [29,32] after introducing trap profiles as close as possible to those extracted from the Si-SiO 2 interface trap TCD and measured as in [11,27,31]. These profiles, which have been obtained systematically after assuming that the trap cross section decreases exponentially with the parameter that governs capture (the distance between a trap and the Si-SiO 2 interface in case of pure tunneling normalized with regard to the tunnel attenuation length, λ e or λ h ), are composed of an exponential decrease in trap concentration, N t , from the faster to the slower interface traps followed by a plateau for even slower or oxide traps, i.e.…”