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Since the 1940s, infrared (IR) detection and imaging at wavelengths in the two atmospheric windows of 3 to 5 and 8 to 14 μm has been extensively researched. Through several generations, these detectors have undergone considerable developments and have found use in various applications in different fields including military, space science, medicine and engineering. For the most recently proposed generation, these detectors are required to achieve high-speed detection with spectral and polarization selectivity while operating at room temperature. Antenna coupled IR detectors appear to be the most promising candidate to achieve these requirements and has received substantial attention from research in recent years. This paper sets out to present a review of the antenna coupled IR detector family, to explore the main concepts behind the detectors as well as outline their critical and challenging design considerations. In this context, the design of both elements, the antenna and the sensor, will be presented individually followed by the challenging techniques in the impedance matching between both elements. Some hands-on fabrication techniques will then be explored. Finally, a discussion on the coupled IR detector is presented with the aim of providing some useful insights into promising future work.

The gap between on-chip and off-chip communication speed has become wider as the IC process technology continues to shrink in order to increase the chip performance. The speed of on-chip circuit has outperformed the off-chip communication speed. Therefore, the performance threshold of a system which consists of multiple IC's is limited by the off-chip communication speed. I/O interfaces such as PCI-Express, USB 3.0, and DDR3 are designed to bridge the gap by introducing high-speed transceiver system which typically operates at Giga-Hertz range. However, legacy copper interconnect on a motherboard backplane cannot support data rate. As a result, integrity of the signal is impaired with nonideal effects introduced by the channel. Continuous-Time Linear Equalizer (CTLE) is used at the receiver front-end to compensate the high-frequency losses introduced by the channel. The implementation of CTLE is normally limited to first-order. Second-order CTLE offers the advantage of incremental peaking gain when dealing with channel of high losses. Therefore, in this paper, the characteristics and theoretical circuit analysis of first-order and second-order CTLEs are presented. Both equalizers are designed to address a 5-Gb/s data rate transmission. An arbitrary 20-inch channel is used as test bench to compare the performance of the two equalizers. Simulation results show improvement in receive eye voltage opening and insertion loss for second-order CTLE but with degradation in terms of receive eye time opening, jitter, and amplitude noise.

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This paper presents a dual-stage LNA design which is enhanced for gain, linearity and noise figure under a certain power constraint. The LNA benefits from an inductivelydegenerated cascode amplifier in the first stage which is followed by a common-source amplifier as the second stage. Two techniques are used to improve the linearity of this 24-dB gain LNA while maintaining the noise figure equal to 2 dB. An input 1-dB gain compression point of -21 dBm was achieved at 2.45-GHz operating frequency. The 0.13-μm CMOS LNA draws a 4-mA current from a 1.2-volt power supply.