Comparison of receiver equalization using first-order and second-order Continuous-Time Linear Equalizer in 45 nm process technology

Lee, C. H.; Mustaffa, Mohd Tafir; Chan, Ken

doi:10.1109/icias.2012.6306122

Cited by 16 publications

(8 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A CTLE is a high pass filter which ideally has a frequency response which is inverse of the frequency response of the communication link [5], [10]. The main advantage of the CTLE is that it mitigates long-term ISI and can nullify both pre-cursor and post-cursor ISI.…”

Section: Conventional Common Source Ctlementioning

confidence: 99%

An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation

Duvvuri

Pasupureddi

2016

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

View full text Add to dashboard Cite

This work presents a first common gate continuous time linear equalizer (CG-CTLE) with charge mode adaptation in 1.1 V, 65 nm CMOS technology. The proposed equalizer is realized with a common gate topology and offers an input impedance of 50 Ω. It also acts as a first stage of current mode receiver and is made adaptive to varying channel loss. Therefore, the need for an external termination to avoid reflections and the need for a trans-impedance amplifier as receiver's first stage is eliminated. The proposed CG-CTLE is compared with conventional common source (CS) CTLE and it outperforms CS-CTLE in terms of bandwidth and bit error rate (BER) for the same targeted output signal swing and power consumption. The post layout performance results show that it offers an input impedance of 44.6 Ω, input referred noise of 19.6 pA/ √ Hz, BER = 10 −13 and consumes 13.9 mW power while operating at a data rate of 15 Gbps over a 7.5 inch FR4 PCB trace.

show abstract

Section: Conventional Common Source Ctlementioning

confidence: 99%

An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation

Duvvuri

Pasupureddi

2016

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

View full text Add to dashboard Cite

show abstract

“…e common structure of conventional CTLE is capacitive degenerated di erential pair [7], as shown in Figure 6(a). e transfer function is given by…”

Section: Ctlementioning

confidence: 99%

A 1.25–12.5 Gbps Adaptive CTLE with Asynchronous Statistic Eye-Opening Monitor

Cai

Zhao

Zhou

2018

Journal of Electrical and Computer Engineering

View full text Add to dashboard Cite

The equalization of a large attenuation signal and multirate communication in high-speed serial interface is hard to balance. To overcome this difficulty, an adaptive equalization system with optimized eye-opening monitor is proposed. The designed eye-opening monitor is based on the asynchronous statistic eye diagram tracking algorithm, and the eye diagram is obtained by undersampling with the low-speed asynchronous clock. With the eye-opening monitor into the adaptive loop, an adaptive equalization system combined with continuous-time linear equalization (CTLE) is completed. And the inductor peaking technology is used to improve the capacity of compensation. With SMIC 28 nm CMOS process to achieve the overall design, the power consumption and core chip area are 12 mW @ 12.5 Gbps and 0.12 mm2, respectively. And postsimulation results show that it can offer compensation from 6 to 21 dB for 1.25–12.5 Gbps range of receiving data, which achieves a large range of data rate and channel loss, and its power efficiency is 0.046 pJ/bit/dB for the worst case, which is better than most previous works.

show abstract

“…The CTLE can improve the signal integrity by raising the high-frequency component of the signal [3,4,5]. However, while the CTLE amplifies the high-frequency component of the signal, noise and crosstalk are potentially amplified.…”

Section: Introductionmentioning

confidence: 99%

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

Zhang

Yang

2020

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents a 36 Gb/s receiver equalizer including an adaptive continuous time linear equalizer (CTLE), which is based on slope detection and a half-rate speculative decision feedback equalizer (DFE) in 0.13 µm BiCMOS technology for high speed serial link. The CTLE with middle frequency compensation can not only adjust the ratio of high frequency and low frequency components adaptively, but also provide a small amount of equalization to middle frequency range. A half-rate speculative DFE, which is connected to the back of the CTLE, can satisfy the time constraints and eliminate the residual intersymbol interference. The chip area including pads is about 1.2 mm 2 and the power consumption is about 750 mW under 3.3 V power supply. Measurement results show that the receiver chip can effectively equalize 24 dB loss at Nyquist frequency and a clear eye diagram can be captured at 36 Gb/s.

show abstract

Comparison of receiver equalization using first-order and second-order Continuous-Time Linear Equalizer in 45 nm process technology

Cited by 16 publications

References 8 publications

An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation

An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation

A 1.25–12.5 Gbps Adaptive CTLE with Asynchronous Statistic Eye-Opening Monitor

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

Contact Info

Product

Resources

About