SUMMARYToday the All Digital Phase-Locked Loop (ADPLL) is applied in many fields. However, previously proposed ADPLLs did not simultaneously implement a wide lock-in range and a fast pull-in. The proposed Dividing ratio Changeable ADPLL (DCPLL) is a method for automatically changing the dividing ratio of the counter in response to the frequency of the input signal and can obtain an extremely wide lock-in range. The output jitter will always be three or fewer pulses of the fast reference clock. By performing remainder control of the dividing ratio during multiplication, an output signal that is a multiple of the constant pulse interval and has jitter characteristics equivalent to the basic operation can be obtained. Furthermore, the initial pull-in is finished in one period of the input signal, which is the shortest time. Consequently, since a wide lock-in range and a fast pull-in can be simultaneously achieved, this DCPLL has many general-purpose applications and is effective in the reference clock source in all types of portable devices and in bit synchronization in data communication.
SUMMARY
Recently, a signal processing using positive and negative edges of clock is used by memory and various digital devices to improve performance of digital circuits. In a signal processing using double edges, 50% duty cycle of an output signal of clock generator is an important factor. In this paper, we propose the programmable divider with which we always obtain the output signal of 50% duty cycle unrelated to the division ratio. The circuit configuration of this divider is very simple, and the operation is stable regardless of the increase in the division ratio. Also, when the proposed divider was included in the division ratio changeable‐digital phase locked loop (DC‐PLL), the output signal is always kept to 50% duty cycle regardless of the frequency of input signal. In experimental results using a field programmable gate array, we confirmed that this DC‐PLL has the expected characteristics for phase error, lock‐in range, and initial pull‐in.
SUMMARYSince phase-locked loops (PLL) are used in the clock extraction of digital communications and high-density digital recording, it is required to have simultaneously low jitter, fast pull-in, and wide lock-in range characteristics. However, in the case of the conventional dividing ratio changeable digital PLL based on phase state memory and double clock-edge detection (PM-DCPLL), the output jitter in the steady state becomes no less than half the pulse width of the base clock controlling the loop, and the upper bound frequency of the lock-in range is limited accordingly. In this paper, we propose a dividing ratio changeable digital phaselocked loop (MC-DCPLL) with low jitter, wide lock-in range, and fast pull-in characteristics using a multiphase clock divider. Since the output jitter of this circuit is one phase difference of the multiphase clock in steady state, the circuit can reduce the output jitter to 1/k of that of a conventional PM-DCPLL when a k phase clock is used. Therefore, the upper bound frequency becomes k times that of a conventional PM-DCPLL. Furthermore, the initial pull-in is completed in one period of the input signal by using the initial pull-in circuit.
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