A Programmable Divider with 50% Duty Cycle Unrelated to Dividing Cycle and Its Application to PLL

Abstract

SUMMARY Recently, a signal processing using positive and negative edges of clock is used by memory and various digital devices to improve performance of digital circuits. In a signal processing using double edges, 50% duty cycle of an output signal of clock generator is an important factor. In this paper, we propose the programmable divider with which we always obtain the output signal of 50% duty cycle unrelated to the division ratio. The circuit configuration of this divider is very simple, and the operation is stable regardless of the increase in the division ratio. Also, when the proposed divider was included in the division ratio changeable‐digital phase locked loop (DC‐PLL), the output signal is always kept to 50% duty cycle regardless of the frequency of input signal. In experimental results using a field programmable gate array, we confirmed that this DC‐PLL has the expected characteristics for phase error, lock‐in range, and initial pull‐in.

Multiple‐frequency digital phase‐locked loop based on multiphase clock divider with constant pulse interval

“…In so doing, the number of multiphase clock ticks divided by 1 + 1/k in the next cycle becomes n − 1; that is, phase error is cleared. When phase error is big, the same operation is repeated; at the moment t 1 , U/D-counter1 counts down by set signal of U/D-counter2, output signal frequency grows according to Equation (2), and phase error is cleared. On the other hand, when the input signal lags in phase as compared to output signal, the phase comparator issues lag signal, and U/D-counter1 counts up; thus, the number of multiphase clock ticks divided by 1 + 1/k in the next cycle becomes n + 1; the same operation is repeated when phase error is big.…”

“…As regards clock pulse interval, increasingly more systems have employed signal processing using both rising and falling edges of clock signals; in this case, clock generation with a duty ratio of 50% is very important. 2 As regards system safety, clock-timing adjustment has increasing influence as systems are digitized, and stable clock generation is required. As regards versatility, development of clock generation circuits for every individual system adds to cost; therefore, wideband generation circuits are needed.…”

“…To achieve this goal, clock signals must be generated quickly when systems recover. As regards clock pulse interval, increasingly more systems have employed signal processing using both rising and falling edges of clock signals; in this case, clock generation with a duty ratio of 50% is very important . As regards system safety, clock‐timing adjustment has increasing influence as systems are digitized, and stable clock generation is required.…”