A dividing ratio changeable digital PLL with low jitter using a multiphase clock divider

Abstract

SUMMARYSince phase-locked loops (PLL) are used in the clock extraction of digital communications and high-density digital recording, it is required to have simultaneously low jitter, fast pull-in, and wide lock-in range characteristics. However, in the case of the conventional dividing ratio changeable digital PLL based on phase state memory and double clock-edge detection (PM-DCPLL), the output jitter in the steady state becomes no less than half the pulse width of the base clock controlling the loop, and the upper bound frequency of the lock-in range is limited accordingly. In this paper, we propose a dividing ratio changeable digital phaselocked loop (MC-DCPLL) with low jitter, wide lock-in range, and fast pull-in characteristics using a multiphase clock divider. Since the output jitter of this circuit is one phase difference of the multiphase clock in steady state, the circuit can reduce the output jitter to 1/k of that of a conventional PM-DCPLL when a k phase clock is used. Therefore, the upper bound frequency becomes k times that of a conventional PM-DCPLL. Furthermore, the initial pull-in is completed in one period of the input signal by using the initial pull-in circuit.

Multiple‐frequency digital phase‐locked loop based on multiphase clock divider with constant pulse interval

“…Multiphase clock DCPLL (MC-DCPLL) using multiphase clock as fixed reference clock instead of conventional single-phase clock was proposed to solve this problem. 10 MC-DPLL can implement a steady-state output jitter within one phase difference in multiphase clock; moreover, lock-in range could be extended as compared to DCPLL at same setting of maximum-frequency change rate. Thus, the upper frequency limit can be set higher, which is a big step toward realization of versatile DPLL.…”

“…However, influence of output jitter increases with frequency of input signal, and an upper limit imposed on frequency restricts the application scope. Multiphase clock DCPLL (MC‐DCPLL) using multiphase clock as fixed reference clock instead of conventional single‐phase clock was proposed to solve this problem . MC‐DPLL can implement a steady‐state output jitter within one phase difference in multiphase clock; moreover, lock‐in range could be extended as compared to DCPLL at same setting of maximum‐frequency change rate.…”