All digital dividing ratio changeable type phase‐locked loop with a wide lock‐in range

Abstract

SUMMARYToday the All Digital Phase-Locked Loop (ADPLL) is applied in many fields. However, previously proposed ADPLLs did not simultaneously implement a wide lock-in range and a fast pull-in. The proposed Dividing ratio Changeable ADPLL (DCPLL) is a method for automatically changing the dividing ratio of the counter in response to the frequency of the input signal and can obtain an extremely wide lock-in range. The output jitter will always be three or fewer pulses of the fast reference clock. By performing remainder control of the dividing ratio during multiplication, an output signal that is a multiple of the constant pulse interval and has jitter characteristics equivalent to the basic operation can be obtained. Furthermore, the initial pull-in is finished in one period of the input signal, which is the shortest time. Consequently, since a wide lock-in range and a fast pull-in can be simultaneously achieved, this DCPLL has many general-purpose applications and is effective in the reference clock source in all types of portable devices and in bit synchronization in data communication.

A dividing ratio changeable digital PLL with low jitter using a multiphase clock divider

“…In this method, the previous period's phase control state is memorized and used for phase control in the next period, and the rise and fall of the reference clock are utilized. As a result, the output jitter in steady state was reduced to half the pulse width of the reference clock, and the upper bound frequency of the synchronization range was extended by a factor of 6 compared to the previous report [8].…”

“…Aiming at a wide synchronization range and fast pull-in with a very simple circuit configuration, the authors proposed a dividing ratio changeable digital PLL (DCPLL) in which the frequency dividing ratio not was fixed but could be adjusted automatically to the input signal [8]. The problem was that output jitter occurred for 3 pulse widths of the reference clock in steady state, which restricted the upper bound frequency of the synchronization range.…”

A dividing ratio changeable digital PLL based on phase state memory and double clock‐edge detection

“…Therefore, the output jitter of the PM-DCPLL in the steady state is a half pulse width of the base clock at all times. The output jitter of a conventional-type DCPLL occurs at three pulse widths of the base clock [6], and as a result, the output jitter is reduced to 1/6 by comparison.…”

“…When multiplication is performed in a conventional DPLL, in order to reduce the output jitter that increases in proportion to the multiplication ratio, a configuration is used in which the value of the U/D-counter representing the dividing ratio of several periods among the low-multiplication output signal is set to +1 using a dividing ratio remainder compensation circuit [6]. However, there remains the problem of the signal controlled to +1 being concentrated in the initial few periods of the multiplication signal in the conventional configuration.…”

“…Improvements in one or two of the three areas have been made, but a circuit that satisfies all three characteristics does not exist. The dividing ratio digital PLL (DCPLL) [6] and a multiplication-type DPLL using a ring-delay line [7] are new methods that have appeared in recent years.…”