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Concerning thermomechanically induced failures, such as metal line deformation and passivation cracks, there is a practicable way to achieve the zero-defect limit of plasticencapsulated power devices. This limit can be reached by evaluating the influence of the major components involved and, consequently, by selecting the appropriate materials and measures. On the other hand, the interdependence between all components must always be kept in mind, i.e., chip and package have to be regarded as an entity. An important finding was that applying simply one improvement step will not necessarily lead to the desired goal. Only the implementation of all improvement steps considering their interdependence is the key for the perfect overall system chip and package. In Part I of this series of papers, the yield stress of the power metallization is shown to play a crucial role for the generation of metal deformation and passivation cracks. Understanding the ratcheting mechanism led to the development of a new layered metallization material with a distinctly increased yield stress, resulting in a considerably reduced failure generation.

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Self-heating can lead to excessive temperatures in large power DMOS transistors, thus restricting their safe operating area (SOA). To explore that limit, the device temperature must be known with sufficient accuracy, which is difficult in advanced BCD technologies. This is because standard measurement methods such as infrared thermography do not show the true device temperature. Also, most (electro-)thermal simulation approaches have not been experimentally verified close to the SOA limits.In this work, a test chip with novel temperature sensors embedded inside the DMOS cell array will be used for accurate measurements of the device temperature. Moreover, a 3-D numerical temperature simulator is extended to correctly consider the temperature-dependent DMOS behavior. Thus, electro-thermal coupling is taken into account while simultaneously calculating the temperatures with high spatial resolution.The validity of the simulator will be demonstrated experimentally by comparison to measurements for temperatures exceeding 500 • C, up to the onset of thermal runaway.

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