Measurement and Simulation of Self-Heating in DMOS Transistors up to Very High Temperatures

Abstract

Self-heating can lead to excessive temperatures in large power DMOS transistors, thus restricting their safe operating area (SOA). To explore that limit, the device temperature must be known with sufficient accuracy, which is difficult in advanced BCD technologies. This is because standard measurement methods such as infrared thermography do not show the true device temperature. Also, most (electro-)thermal simulation approaches have not been experimentally verified close to the SOA limits.In this work, a test chip with novel temperature sensors embedded inside the DMOS cell array will be used for accurate measurements of the device temperature. Moreover, a 3-D numerical temperature simulator is extended to correctly consider the temperature-dependent DMOS behavior. Thus, electro-thermal coupling is taken into account while simultaneously calculating the temperatures with high spatial resolution.The validity of the simulator will be demonstrated experimentally by comparison to measurements for temperatures exceeding 500 • C, up to the onset of thermal runaway.

Active cycling reliability of power devices: Expectations and limitations

“…However, the feedback loop of temperature on the device parameters has to be implemented correctly. And calibration is mandatory [3]. If done properly, simulation provides information on the physical behavior of the device in a manner that is not accessible by measurement.…”

Modeling of highly anisotropic microstructures for electro-thermal simulations of power semiconductor devices

“…Generally, the representative model of such devices can be described by finite elements [3], finite differences [4], lumped electrical and thermal parameters [5], etc. In all cases, in order to keep the simulation's computational effort to a reasonable level, those models normally do not describe all the small geometrical details present in the device cell.…”

High temperature on-wafer measurement structure for DMOS characterization

“…For this, 3-D electro-thermal simulations have to be performed, requiring correct modeling for operating conditions corresponding to thermal runaway [1,2]. This includes prediction of thermal runaway behavior caused by the parasitic NPN inherent to the DMOS transistor [3].…”

“…Its contribution is important at temperatures exceeding 400ºC. Thus appears the necessity of calibrated DMOS models that are accurate at very high temperatures up to 600ºC [1].…”