Design of notched gate processes in high density plasmasOn the origin of the notching effect during etching in uniform high density plasmas Numerical simulation was used to study both surface charging and ion trajectory distortion during submicron patterning in high density plasma etching. The plasma was assumed uniform and the cause for the surface charging was the directionality difference between ions and electrons. The role of ion transit time effects on the ion energy distribution function was also considered, while the effect of discharging currents such as through insulators was not included. Using a Monte Carlo sheath simulator, a Poisson equation solver, and an ion/electron trajectory simulator, the steady state potential distribution and ion trajectories were calculated for various line-and-space structures and plasma conditions where notching, which is a local sidewall etching, has been observed after the overetching part of polysilicon etching processes. The results show significant positive charging at the bottom of high aspect ratio spaces which depends on the ion energy distribution function. Notching at the bottom of an outermost polysilicon line before a wide space is the result of ion deflection toward the line which has the lower potential from receiving more electrons from a side facing the wide space. The simulator was validated using previously reported electron cyclotron resonance etcher notching results. It was found that the calculated potential difference between the bottom of a space and the adjacent line shows the same qualitative dependence on the wide space width as experimental notch depth results show. In addition, these potential differences are large enough to substantially increase the ion flux at regions where notching occurs for the ion energy distribution function for the plasma conditions used. Thus this shows aspect ratio dependent charging effects which are not dependent on initial plasma nonuniformity.

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We demonstrate the smallest FinFET SRAM cell size of 0.063 μm 2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE 2 ) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

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