Abstract:Design of notched gate processes in high density plasmasOn the origin of the notching effect during etching in uniform high density plasmas Numerical simulation was used to study both surface charging and ion trajectory distortion during submicron patterning in high density plasma etching. The plasma was assumed uniform and the cause for the surface charging was the directionality difference between ions and electrons. The role of ion transit time effects on the ion energy distribution function was also consid… Show more
“…The enhanced conductivity can also have beneficial effects on the etching properties of SiO 2 such as reduction of notching, sidewall bowing, and trenching. 17 FIG. 7.…”
Section: Measurements Of the J -V Characteristics Of Thin Sio 2 Lmentioning
In this article we report a method for in situ electrical characterization of dielectric thin films under direct exposure to plasma in an electron-cyclotron-resonance etcher. This method is based on the development of a special test structure that allows for the measurement of the influence of plasma vacuum-ultraviolet ͑VUV͒ radiation on the electrical conductivity of thin dielectric layers. Results show that the measured conductivity of SiO 2 layers temporarily increases during exposure to argon and oxygen plasmas, with controlled VUV emission. Based on the measurements made through this method, a model of the VUV-induced conductivity of SiO 2 is developed. These measurements are very important for plasma processing of semiconductor devices, because the temporary increase in the conductivity of these layers upon exposure to processing plasmas can decrease the plasma-induced charging of these dielectric layers depending on the intensity of the plasma VUV emission. This can have an impact on the properties and reliability of processed devices.
“…The enhanced conductivity can also have beneficial effects on the etching properties of SiO 2 such as reduction of notching, sidewall bowing, and trenching. 17 FIG. 7.…”
Section: Measurements Of the J -V Characteristics Of Thin Sio 2 Lmentioning
In this article we report a method for in situ electrical characterization of dielectric thin films under direct exposure to plasma in an electron-cyclotron-resonance etcher. This method is based on the development of a special test structure that allows for the measurement of the influence of plasma vacuum-ultraviolet ͑VUV͒ radiation on the electrical conductivity of thin dielectric layers. Results show that the measured conductivity of SiO 2 layers temporarily increases during exposure to argon and oxygen plasmas, with controlled VUV emission. Based on the measurements made through this method, a model of the VUV-induced conductivity of SiO 2 is developed. These measurements are very important for plasma processing of semiconductor devices, because the temporary increase in the conductivity of these layers upon exposure to processing plasmas can decrease the plasma-induced charging of these dielectric layers depending on the intensity of the plasma VUV emission. This can have an impact on the properties and reliability of processed devices.
“…This effect leads to a number serious plasma process induced damage problems such as bowing, trenching, reactive ion etching lag, and notching [48]. Surface charging has been a subject of numerous papers [49][50][51] including charging induced damage in [52][53][54][55][56]. Since the finite difference method is not useful when the geometry of the problem is irregular, the finite elements method has been used for solving Poisson equation describing the electric field in the feature.…”
Abstract:This article contains a broad overview of etch process as one of the most important top-down technologies widely used in semiconductor manufacturing and surface modification of nanostructures. In plasma etching process, the complexity comes from the introduction of new materials and from the constant reduction in dimensions of the structures in microelectronics. The emphasis was made on two types of etching processes: dry etching and wet etching illustrated by three dimensional (3D) simulation results for the etching profile evolution based on the level set method. The etching of low-k dielectrics has been demonstrated via modelling the porous materials. Finally, simulation results for the roughness formation during isotropic etching of nanocomposite materials as well as smoothing of the homogeneous materials have also been shown and analyzed. Simulation results, presented here, indicate that with shrinking microelectronic devices, plasma and wet etching interpretative and predictive modeling and simulation have become increasingly more attractive as a tool for design, control and optimization of plasma reactors.
PACS (2008):81.05. Rm, 85.40.Hp, 85.85.+j, 87.10.Ed
“…1 The prevailing cause of the notching effect is believed to be the charging of the exposed SiO 2 surface at the bottom of cleared trenches between gate electrodes, which can lead to ion trajectory bending and lateral sidewall etching. 4,5 When SiO 2 surface charging is reduced, e.g., by decreasing the thickness of the gate oxide so that electron tunneling becomes important, notching is eliminated. 2,6 Surface charging could also be reduced by surface conduction.…”
Surface charge dissipation on insulator surfaces can reduce local charging potentials thereby preventing ion trajectory deflection at the bottom of trenches that leads to lateral sidewall etching ͑notching͒. We perform detailed Monte Carlo simulations of pattern-dependent charging during etching in high-density plasmas with the maximum sustainable surface electric field as a parameter. Significant notching occurs for a threshold electric field as low as 0.5 MV/cm or 50 V/m, which is reasonable for the surface of good insulators. The results support pattern-dependent charging as the leading cause of notching and suggest that the problem will disappear as trench widths are reduced.
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