Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

Liu, Q.; Yagishita, Akira; Loubet, N.; Khakifirooz, A.; Kulkarni, P.; Yamamoto, Tsuyoshi; Cheng, K.; Fujiwara, M.; Cai, Jin; Dorman, D.; Mehta, S.; Khare, Prasanna; Yako, Koichi; Zhu, Yuhao; Mignot, Sylvie; Kanakasabapathy, S.; Monfray, S.; Bœuf, F.; Koburger, Charles W.; Sunamura, H.; Ponoth, S.; Reznicek, A.; Haran, Bala; Upham, A.; Johnson, Rob; Edge, L. F.; Kuss, J.; Levin, T. M.; Berliner, N.; Leobandung, E.; Skotnicki, T.; Hane, M.; Bu, H.; Ishimaru, K.; Kleemeier, W.; Takayanagi, Motowo; Doris, B.; Sampson, R.

doi:10.1109/vlsit.2010.5556120

Cited by 63 publications

(35 citation statements)

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“…These devices feature a BOX of 25 nm down to a few nanometer that, when combined with UTB, results in very good electrostatic control of the gate and reduced variability originating from RDF effects [32]- [36]. UTB and BOX (UTBB) device performance is enhanced compared to extremely thin SOI (ETSOI) [37], both in terms of short channel effect control and S/D coupling due to the use of the thin BOX, and especially when combined with a ground plane doping scheme [38].…”

Section: Silicon-on-insulator and Shallow Trench Isolationmentioning

confidence: 99%

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Chatzikyriakou

Morgan

Groot

2018

IEEE Trans. Electron Devices

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-From man-made satellites and interplanetary missions to fusion power plants, electronic equipment that needs to withstand various forms of irradiation is an essential part of their operation. Examination of total ionizing dose (TID) effects in electronic equipment can provide a thorough means to predict their reliability in conditions where ionizing dose becomes a serious hazard. In this paper, we provide a historical overview of logic and memory technologies that made the biggest impact both in terms of their competitive characteristics and their intrinsically hardened nature against TID. Further to this, we also provide guidelines for hardened device designs and present the cases where hardened alternatives have been implemented and tested in the lab. The technologies that we examine range from silicon-on-insulator and FinFET to 2-D semiconductor transistors and resistive random access memory.Index Terms-2-D semiconductor, carbon, CMOS, deep submicrometer, FinFET, graphene, MoS2, resistive random access memory (RRAM), silicon-on-insulator (SOI), thin film, total ionizing dose (TID), ultrathin buried oxide (UTBOX).

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Section: Silicon-on-insulator and Shallow Trench Isolationmentioning

confidence: 99%

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Chatzikyriakou

Morgan

Groot

2018

IEEE Trans. Electron Devices

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“…FDSOI is an advanced planar technology [Liu et al 2010]. Figure 2 depicts a cross-section of a UTBB FDSOI device and highlights the main technological features.…”

Section: Low-power High-performances Devices: Towards Thin Devicesmentioning

confidence: 99%

“…Such thin channel enables a good electrostatic control with, for instance, a low drain induced barrier lowering (DIBL) value [Khakifirooz et al 2012] by cutting deep field lines originating from the drain. In a 28nm UTBB FDSOI node, the silicon film thickness T SI is approximately 8-9nm [Liu et al 2010].…”

Section: Low-power High-performances Devices: Towards Thin Devicesmentioning

confidence: 99%

A Survey on Low-Power Techniques with Emerging Technologies

Gaillardon

Beigné

Lesecq

et al. 2015

J. Emerg. Technol. Comput. Syst.

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Nowadays, power consumption is one of the main limitations of electronic systems. In this context, novel and emerging devices provide new opportunities to extend the trend toward low-power design. In this survey article, we present a transversal survey on energy-efficient techniques ranging from devices to architectures. The actual trends of device research, with fully depleted planar devices, tri-gate geometries, and gateall-around structures, allows us to reach an increasingly higher level of performance while reducing the associated power. In addition, beyond the simple device property enhancements, emerging devices also lead to innovations at the circuit and architectural levels. In particular, devices whose properties can be tuned through additional terminals enable a fine and dynamic control of device threshold. They also enable designers to realize logic gates and to implement power-related techniques in a compact way unreachable to standard technologies. These innovations reduce power consumption at the gate level and unlock new means of actuation in architectural solutions like adaptive voltage and frequency scaling.

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“…For battery-life limited wireless applications, fully depleted silicon-on-insulator (FDSOI) has emerged as a promising candidate for sub-micrometer technology nodes due to better control over short channel effects [3], [4], performance enhancement capability via back-bias tuning [5], [6], better thermal properties [7], and reduced random dopant fluctuations [8]. With continuous channel length scaling, FDSOI-based CMOS transistors are now becoming an appropriate choice in the Schematic of an FDSOI transistor [17] with an HR substrate without a trap rich layer below BOX.…”

Section: Introductionmentioning

confidence: 99%

RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model

Kushwaha

Khandelwal

Duarte

et al. 2016

IEEE Trans. Microwave Theory Techn.

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In this paper, RF modeling and step-by-step parameter extraction methodology of the BSIM-IMG model are discussed with experimental data. BSIM-IMG is the latest industry standard surface potential based model for fully depleted siliconon-insulator (FDSOI) transistors. The impact of gate, substrate, and thermal networks is demonstrated with S-parameter data, which enable the BSIM-IMG model to capture RF behavior of the FDSOI transistor. The model is validated over a wide range of biases and frequencies and excellent agreement with the experimental data is obtained.Index Terms-BSIM-IMG, compact model, fully depleted silicon-on-insulator (FDSOI), MOSFET, parameter extraction, RF.

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Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

Cited by 63 publications

References 0 publications

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

A Survey on Low-Power Techniques with Emerging Technologies

RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model

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