RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model

Kushwaha, Pragya; Khandelwal, Sourabh; Duarte, Juan Pablo; Hu, Chenming; Chauhan, Yogesh Singh

doi:10.1109/tmtt.2016.2557327

Cited by 37 publications

(8 citation statements)

References 34 publications

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“…From the Fig. 7, at low frequency, due to the influence of dynamic self heating effect, g ds shows an increasing trend, but at about a few GHz, the dynamic self heating effect is suppressed [28], [29]. In the frequency range from 10 9 Hz to 10 10 Hz, the g ds -frequency curves are relatively flat, so the g ds values of all the devices are extracted at 5 GHz in this paper.…”

Section: B Rf Foms and Small-signal Parametersmentioning

confidence: 92%

Characterization of 22 nm FDSOI nMOSFETs With Different Backplane Doping at Cryogenic Temperature

Xie

Wang

et al. 2021

IEEE J. Electron Devices Soc.

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In this work, the electrostatic and radio frequency performances of 22 nm FDSOI nMOSFETs with p-type or n-type doped backplane (BP, highly doped layer of silicon below thin buried oxide) at cryogenic temperatures have been investigated. Greater enhancement of drain current I d , maximum transconductance g m,max and threshold voltage V TH values have been demonstrated at liquid nitrogen temperatures. Furthermore, FDSOI nMOSFETs with n-type BP achieve the maximum transconductance at lower bias voltage and smaller V ZTC , which is mainly due to its small threshold voltage. The variation of threshold voltage of BP-p devices is greater with the decrease of temperature. About 40% improvement of f T and 30% improvement of f max depended on the W f of devices have been shown. Relevant small-signal parameters (e.g., transconductance g m , gate capacitance C gg , gate resistance R g and output conductance g ds ) are also extracted for comparison and analysis. This study presents both 22 nm FDSOI nMOSFETs with p-type or n-type backplane as good candidates for cryogenic applications down to 77 K, and especially, BP-n FDSOI are more suitable for low power operation applications because of their lower threshold voltage. Similar g m.max and the peak values of RF FOMs can be obtained at lower bias voltage compared with BP-p devices.INDEX TERMS Backplane (BP) doping, cryogenic, fully-depleted silicon-on-insulator (FDSOI), RF

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Section: B Rf Foms and Small-signal Parametersmentioning

confidence: 92%

Characterization of 22 nm FDSOI nMOSFETs With Different Backplane Doping at Cryogenic Temperature

Xie

Wang

et al. 2021

IEEE J. Electron Devices Soc.

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“…The overall FE-FDSOI is then modeled by solving the charge balance (Q MOS = P FE *W*L) and voltage balance (V TOTAL = V FE + V MOS ). The FDSOI transistor is modeled using the industry-standard BSIM-IMG model [36], [37]. The effect of BG bias is automatically included in the BSIM model [38].…”

Section: A Our Spice Modeling and Validation Of Fefetmentioning

confidence: 99%

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Kumar

Chatterjee

Thomann

et al. 2023

IEEE Trans. Circuits Syst. I

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Today's data-centric applications are incompatible with the predominant compute-centric computer architectures. The small on-chip memories of compute-centric computer architecture demand many energy-costly data transfers exposing the von-Neumann bottleneck. The Ferroelectric Field-Effect Transistor (FeFET) is an emerging Non-Volatile Memory (NVM) technology enabling novel data-centric architectures that go far beyond von-Nuemann principles. FeFETs are very promising for a wide range of applications starting from on-chip memories to in-memory computing and even neuromorphic computing. Nevertheless, FeFET devices exhibit significant variations that can severely restrict their applicability. Temperature further exacerbates variation effects because it degrades ferroelectric parameters. Hence, it is indispensable to investigate and model design-time variations, run-time variations, and stochastic variations due to spatial fluctuation of ferroelectric domains under different temperatures. Dual-port FeFET has been recently proposed and demonstrated as novel structure that offers for the first time disturb-free read operation along with > 10 larger memory window (MW) compared to conventional FeFETs. However, all of the before-mentioned types of variations are amplified in such a new structure. In this work, the impact of temperature variation is analyzed for dual-port FeFETs for the first time in a cross-layer manner starting from the device level to the circuit/system levels and compared to conventional FeFET.We focus in our analysis on Hyperdimensional Computing (HDC), which is an emerging type of machine learning algorithm, that is being executed on top of FeFET-based in-memory circuits that perform efficient Hamming distance (i.e., similarity) computations. Through our cross-layer framework, we demonstrate the serious impact of variation on FeFET reliability despite the significant increase in the MW that dual-port FeFET offers. Even HDC is affected, despite its remarkable robustness against errors. All in all, our work reveals that a larger MW at the device level does not necessarily translate to benefits at the application level. Hence, investigating and modeling variability effects in a crosslayer manner is indispensable.

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“…The THz research gap in relation to the present [29,31,41,42,43] and forecast [34,35] f max capability of transistor technologies, estimated current state of transistor modeling [44,45] and packaging [38] and reported achieved frequency operation of some THz circuits [1,42,46,47,48,49,50,51,52]. …”

Section: Figurementioning

confidence: 99%

Emerging Transistor Technologies Capable of Terahertz Amplification: A Way to Re-Engineer Terahertz Radar Sensors

Božanić

Sinha

2019

Sensors

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This paper reviews the state of emerging transistor technologies capable of terahertz amplification, as well as the state of transistor modeling as required in terahertz electronic circuit research. Commercial terahertz radar sensors of today are being built using bulky and expensive technologies such as Schottky diode detectors and lasers, as well as using some emerging detection methods. Meanwhile, a considerable amount of research effort has recently been invested in process development and modeling of transistor technologies capable of amplifying in the terahertz band. Indium phosphide (InP) transistors have been able to reach maximum oscillation frequency (fmax) values of over 1 THz for around a decade already, while silicon-germanium bipolar complementary metal-oxide semiconductor (BiCMOS) compatible heterojunction bipolar transistors have only recently crossed the fmax = 0.7 THz mark. While it seems that the InP technology could be the ultimate terahertz technology, according to the fmax and related metrics, the BiCMOS technology has the added advantage of lower cost and supporting a wider set of integrated component types. BiCMOS can thus be seen as an enabling factor for re-engineering of complete terahertz radar systems, for the first time fabricated as miniaturized monolithic integrated circuits. Rapid commercial deployment of monolithic terahertz radar chips, furthermore, depends on the accuracy of transistor modeling at these frequencies. Considerations such as fabrication and modeling of passives and antennas, as well as packaging of complete systems, are closely related to the two main contributions of this paper and are also reviewed here. Finally, this paper probes active terahertz circuits that have already been reported and that have the potential to be deployed in a re-engineered terahertz radar sensor system and attempts to predict future directions in re-engineering of monolithic radar sensors.

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RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model

Cited by 37 publications

References 34 publications

Characterization of 22 nm FDSOI nMOSFETs With Different Backplane Doping at Cryogenic Temperature

Characterization of 22 nm FDSOI nMOSFETs With Different Backplane Doping at Cryogenic Temperature

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Emerging Transistor Technologies Capable of Terahertz Amplification: A Way to Re-Engineer Terahertz Radar Sensors

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