Characterization of 22 nm FDSOI nMOSFETs With Different Backplane Doping at Cryogenic Temperature

Abstract

In this work, the electrostatic and radio frequency performances of 22 nm FDSOI nMOSFETs with p-type or n-type doped backplane (BP, highly doped layer of silicon below thin buried oxide) at cryogenic temperatures have been investigated. Greater enhancement of drain current I d , maximum transconductance g m,max and threshold voltage V TH values have been demonstrated at liquid nitrogen temperatures. Furthermore, FDSOI nMOSFETs with n-type BP achieve the maximum transconductance at lower bias voltage and smaller V ZTC , which is mainly due to its small threshold voltage. The variation of threshold voltage of BP-p devices is greater with the decrease of temperature. About 40% improvement of f T and 30% improvement of f max depended on the W f of devices have been shown. Relevant small-signal parameters (e.g., transconductance g m , gate capacitance C gg , gate resistance R g and output conductance g ds ) are also extracted for comparison and analysis. This study presents both 22 nm FDSOI nMOSFETs with p-type or n-type backplane as good candidates for cryogenic applications down to 77 K, and especially, BP-n FDSOI are more suitable for low power operation applications because of their lower threshold voltage. Similar g m.max and the peak values of RF FOMs can be obtained at lower bias voltage compared with BP-p devices.INDEX TERMS Backplane (BP) doping, cryogenic, fully-depleted silicon-on-insulator (FDSOI), RF

CMOS Scaling Challenges for High Performance and Low Power applications facing Reliability Criteria towards the Decananometer range

“…Figure 2b between the two domains of µeff reduction at 125°C and VT-shift effect at -40°C. Mobility increase at low temperature becomes smaller in short channel due to the reduced neutral defect scattering as shown at liquid nitrogen temperature (77K) [11] . As the performance of CMOS node at Decananometer size is strongly dependent on the process quality and reliability, this can be determined in the following by studying the (time zero) process variability and the aging resistance by using accelerated stressing (section 4) that induces a progressive time variability [12], [13] .…”

“…FDSOI transistor is known to be excellent candidate for digital and analog applications [3] , RF circuits under millimeter range, space and avionics applications [11] . Its structure presents (Figure 1c) an ultrathin body (UTB) on a buried oxide (BOX) that offers many advantages in MOSFET as good electrostatics control, small subthreshold slope value (SS) and short channel effects (SCE) due to limited drain-induced barrier lowering (DIBL) [3] .…”

Design of silicon-on-insulator field-effect transistor using graphene channel to improve short channel effects over conventional devices

“…The model, however, is not examined for temperature change. The performance of FDSOI at cryogenic temperatures was examined by Xie et al [24]. A highly doped backplane below buried oxide is used Improvements are shown in the V th , transconductance, and drain current.…”

Characterisation of Photodiodes in 22 nm FDSOI at 850 nm

“…t BOX , t Si-C , t SOI , t Bulk , and t STI are 20 nm, 6 nm [11], 13 nm, 20 nm, and 220 nm [7], [11], [12] respectively. A common rule of thumb for the NW and PW thicknesses is to take half their minimum lateral length [10].…”

“…MOSIS provides a set of rules that is compatible with many technologies, giving a good overview of what reasonable well dimensions are [13]. The geometric mean of the STI thickness (t STI = 220 nm, lower boundary [7], [11], [12]) and maximum MOSIS Scalable CMOS well thickness (750 nm, upper boundary [13]) gives an estimate for t Well of 406 nm. t DNW is estimated to be 1.13 µm based on the PW and DNW ratio (2.78) from [14].…”