CMOS Scaling Challenges for High Performance and Low Power applications facing Reliability Criteria towards the Decananometer range

Abstract

The huge improvements in integrated circuits manufacturing has faced great challenges between process optimization, performance requirements and the trade-off between low power operation and reliability for long term use. Both the variability at time zero and the time variability due to external constraints and aging phenomena make mandatory the validation of the CMOS technology nodes from device to circuits and products under operation. While High-K Metal-Gate (HKMG) offered good compromises down to 28nm gate-length, the move to Fully Depleted Silicon on Insulator (FDSOI) allows to further scale the dimension down to 14nm effective gate-length with ultra-thin equivalent gate-oxide thickness (EOT) of 1.35 nm. This has been obtained guarantying a small subthreshold slope for switching, small drain-induced barrier lowering (DIBL) for limited short-channel effect (SCE) and excellent current drivability thanks to a proper gate-stack with HfO2/SiON optimization and adapted rapid thermal processing and annealing. We give new insights to determine first the performance with temperature, the process variability impact at time zero and the robustness of CMOS nodes submitted to interface traps, oxide charge and recoverable traps. Their role is analysed using accelerated DC and AC experiments in devices to SRAM cell and array, focusing on the balance between hot-carrier and bias temperature damage. This allows to guaranty the technology robustness, speed performance and limited power consumption for product qualification.

The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms

“…For HCD, the phenomenon involves the breakage of Si-H bonds by high-energy hot carriers, forming interface states that induce degradation in the threshold voltage and mobility [ 56 , 57 , 58 ]. As device nodes advance and carrier energy decreases, electron–electron scattering (EES) and multiple vibration excitation (MVE) mechanisms have been proposed to explain the contributions of low-energy carriers to HCD [ 59 , 60 , 61 ]. Simultaneously, the contribution of oxide trap-induced degradation in HCD becomes more pronounced, especially in FinFET devices, where HCD is considered a combined effect of oxide traps and interface states [ 62 , 63 ].…”