We report low-temperature electronic transport in batch-processed single-walled carbon nanotube (SWNT) field-effect transistors (FETs). SWNTs are in situ synthesized and wired between submicrometer metallic electrodes in a single-step process involving hot-filament-assisted chemical vapor deposition. FETs show a pronounced ambipolar field effect between 1 and 300 K. Moreover, the gate dependence exhibits hysteresis at any temperature because of the extraction and trapping of charges. We find Schottky barriers at the SWNT/metal contact to be responsible for the field effect. Below 30 K, potential barriers along the SWNT induce a Coulomb blockade at low drain-source bias, leading to the suppression of the field-effect gain and inducing fluctuations in the transconductance.

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We demonstrate epitaxially grown high-quality pure germanium (Ge) on bulk silicon (Si) substrates by ultra-high-vacuum chemical vapor deposition (UHVCVD) without involving growth of thick relaxed SiGe buffer layers. The Ge layer is grown on thin compressively strained SiGe layers with rapidly varying Ge mole fraction on Si substrates resulting in several SiGe interfaces between the Si substrate and the pure Ge layer at the surface. The presence of such interfaces between the Si substrate and the Ge layer results in blocking threading dislocation defects, leading to a defect-free pure Ge epitaxial layer on the top. Results from various material characterization techniques on these grown films are shown. In addition, capacitance-voltage (CV) measurements of metal-oxide-semiconductor (MOS) capacitors fabricated on this structure are also presented, showing that the grown structure is ideal for high-mobility metal-oxide-semiconductor field-effect transistor applications.

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Eight strained-Si (sSi) on SiGe heterostructures with 8, 13, 25, or 40 nm sSi on top of 300 or 600 nm Si0.77Ge0.23 buffer have been prepared by chemical vapor deposition and examined by preferential defect etching and Raman spectroscopy. Defect etching revealed that threading dislocations (TDs) in the supercritical thickness sSi samples are more evenly distributed, while they are severely trapped inside TD pileups in the subcritical thickness sSi samples. It is proposed that relaxation of the supercritical sSi layer, which is realized by TD gliding under a tensile stress, helps to breakup those pileups formed under a compressive stress. Defect etching revealed a TD density of (3–5)×106 cm−2, and no dependence on the sSi or SiGe thickness was observed. Raman spectroscopy revealed that the relaxation degree of the 300 nm SiGe layer decreases from 80% to 67% with the sSi layer increasing from 8 to 40 nm. This suggests a continuous relaxation of the highly compressively strained, thin SiGe buffer during or even after sSi growth, and its gradual suppression by the presence of a tensile strained sSi layer. The 600 nm SiGe buffer has an ∼82% relaxation for all sSi thickness, suggesting that its relatively small residual strain cannot support any further relaxation after switching to sSi growth and consequently the absence of any dependence on sSi thickness. Based on these observations, we suggest that an in situ thermal annealing prior to the sSi growth will help to enhance the strain relaxation of thin SiGe buffers.

We demonstrate ultra-thin (<150 nm) Si 1)x Ge x dislocation blocking layers on Si substrates used for the fabrication of tensile-strained Si N channel metal oxide semiconductor (NMOS) and Ge P channel metal oxide semiconductor (PMOS) devices. These layers were grown using ultra high vacuum chemical vapor deposition (UHVCVD). The Ge mole fraction was varied in rapid, but distinct steps during the epitaxial layer growth. This results in several Si 1)x Ge x interfaces in the epitaxially grown material with significant strain fields at these interfaces. The strain fields enable a dislocation blocking mechanism at the Si 1)x Ge x interfaces on which we were able to deposit very smooth, atomically flat, tensile-strained Si and relaxed Ge layers for the fabrication of high mobility N and P channel metal oxide semiconductor (MOS) devices, respectively. Both N and P channel metal oxide semiconductor field effect transister (MOSFETs) were successfully fabricated using high-k dielectric and metal gates on these layers, demonstrating that this technique of using ultra-thin dislocation blocking layers might be ideal for incorporating high mobility channel materials in a conventional CMOS process.