A leading edge 90 nm technology with 1.2 nm physical gate oxide, SO nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k CDO for high performance dense logic is presented. Strained silicon is used to increase saturated NMOS and PMOS drive currents by 10-20% and mobility by > 50%. Aggressive design rules and unlanded contacts offer a l.0pm2 6-T S R A M cell using 193nm lithography. IntroductionThe power dissipation of modern microprocessors has been rapidly increasing, driven by increasing transistor count and clock frequencies. The rapidly increasing power has occurred even though the power per gate switching transition has decreased approximately (0.7)' per technology node due to voltage scaling and device area scaling. Figure 1 shows these trends for Intel's microprocessors and CMOS logic technology generations. In this paper we describe a 90 nm generation technology designed for high speed and low power operation. Strained silicon channel transistors are used to obtain the desired performance at 1.0V to 1.2V operation. renw 5 B 0 n 1 0 0 0 0~ Pentiud U) E 1.5 1 0.8 0.6 0.35 0.25 0.18 0.13 Technology (pm) Figure 1: Power and transistor switching energy trends. procesS Flow and Technology FeaturesFront-end technology features include shallow trench isolation, retrograde wells, shallow abrupt sourceldrain extensions, halo implants, deep sourcddrain, and nickel salicidation. N-wells and P-wells are formed with deep phosphw rous and shallow arsenic implants, and boron implants respectively. The trench isolation is 400 nm deep to provide robust inma-and inter-well isolation for N+ to P+ spacing below 240 nm while maintaining low junction capacitance. Sidewall spacers are formed with CVD Si,N4 deposition, followed by etch-back. Shallow sourcedrain extension regions are formed with arsenic for NMOS and boron for PMOS. Nisi is formed on poly-silicon gate and source-drain regions to provide low contact resistance.

The temperature dependence of the field effect mobility was measured for solution-grown single-crystal Ge nanowires. The nanowires were synthesized in hexane from diphenylgermane by the supercritical fluid-liquid-solid process using gold nanocrystals as seeds. The nanowires were chemically treated with isoprene to passivate their surfaces. The electrical properties of individual nanowires were then measured by depositing them on a Si substrate, followed by electrical connection with Pt wires using focused ion beam assisted chemical vapor deposition. The nanowires were positioned over TaN or Au electrodes covered with ZrO2 dielectric that were used as gates to apply external potentials to modulate the conductance. Negative gate potentials increased the Ge nanowire conductance, characteristic of a p-type semiconductor. The temperature-dependent source/drain current-voltage measurements under applied gate potential revealed that the field effect mobility increased with increasing temperature, indicating that the carrier mobility through the nanowire is probably dominated either by a hopping mechanism or by trapped charges in fast surface states.

We report the growth and characterization of thin (<35nm) germanium-carbon alloy (Ge1−xCx) layers grown directly on Si by ultrahigh-vacuum chemical vapor deposition, with capacitance-voltage and leakage characteristics of the first high-κ/metal gate metal-oxide-semiconductor (MOS) capacitors fabricated on Ge1−xCx. The Ge1−xCx layers have an average C concentration of approximately 1at.% and were obtained using the reaction of CH3GeH3 and GeH4 at a deposition pressure of 5mTorr and growth temperature of 450°C. The Ge1−xCx films were characterized by secondary ion mass spectrometry, atomic force microscopy, x-ray diffraction, and cross-sectional transmission electron microscopy. A modified etch pit technique was used to calculate the threading dislocation density. The x-ray diffraction results showed that the Ge1−xCx layers were partially relaxed. The fabricated MOS capacitors exhibited well-behaved electrical characteristics, demonstrating the feasibility of Ge1−xCx layers on Si for future high-carrier-mobility MOS devices.

We demonstrate epitaxially grown high-quality pure germanium (Ge) on bulk silicon (Si) substrates by ultra-high-vacuum chemical vapor deposition (UHVCVD) without involving growth of thick relaxed SiGe buffer layers. The Ge layer is grown on thin compressively strained SiGe layers with rapidly varying Ge mole fraction on Si substrates resulting in several SiGe interfaces between the Si substrate and the pure Ge layer at the surface. The presence of such interfaces between the Si substrate and the Ge layer results in blocking threading dislocation defects, leading to a defect-free pure Ge epitaxial layer on the top. Results from various material characterization techniques on these grown films are shown. In addition, capacitance-voltage (CV) measurements of metal-oxide-semiconductor (MOS) capacitors fabricated on this structure are also presented, showing that the grown structure is ideal for high-mobility metal-oxide-semiconductor field-effect transistor applications.

No abstract