In this article, a low-power, radiation-hard frontend circuit for monolithic pixel sensors, designed to meet the requirements of low noise and low pixel-to-pixel variability, the key features to achieve high detection efficiencies, is presented.
The MALTA family of depleted monolithic pixel sensors produced in TowerJazz 180 nm CMOS technology target radiation hard applications for the HL-LHC and beyond. Several process modifications and front-end improvements have resulted in radiation hardness >1015 1 MeV neq/cm2 and time resolution below 2 ns, with uniform charge collection and efficiency across the pixel of size 36.4 × 36.4 µm2 with small collection electrode. This contribution will present the comparison of samples produced on high-resistivity epitaxial silicon with Czochralski substrates, before and after neutron irradiation, and results from MALTA2 with a new cascoded front-end flavour that further reduces the RTS noise.
The RD53 collaboration has been working since 2014 on the development of pixel chips for the CMS and ATLAS Phase 2 tracker upgrade. This work has recently led to the development of the RD53B full-scale readout chip which is using the 65nm CMOS process and containing 153600 pixels of 50 × 50 μm
2 The RD53B chip is designed to be robust against the Single Event Effects (SEE), allowing such a complex chip to operate reliably in the hostile environment of the HL-LHC. Different SEE mitigation techniques based on the Triple Modular Redundancy (TMR) have been adopted for the critical information in the chip. Furthermore, the efficiency of this mitigation scheme has been evaluated for the RD53B chip with heavy ion beams in the CYCLONE facility and with a 480 MeV proton beam in TRIUMF facility. The purpose of this paper is to describe and explain all the SEE mitigation strategies used in the RD53B chip, to report and analyze the heavy ions and proton tests results and to estimate the expected Single Event Upset (SEU) rates at the HL-LHC.
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