Single event effects testing of the RD53B chip

Abstract

The RD53 collaboration has been working since 2014 on the development of pixel chips for the CMS and ATLAS Phase 2 tracker upgrade. This work has recently led to the development of the RD53B full-scale readout chip which is using the 65nm CMOS process and containing 153600 pixels of 50 × 50 μm 2 The RD53B chip is designed to be robust against the Single Event Effects (SEE), allowing such a complex chip to operate reliably in the hostile environment of the HL-LHC. Different SEE mitigation techniques based on the Triple Modular Redundancy (TMR) have been adopted for the critical information in the chip. Furthermore, the efficiency of this mitigation scheme has been evaluated for the RD53B chip with heavy ion beams in the CYCLONE facility and with a 480 MeV proton beam in TRIUMF facility. The purpose of this paper is to describe and explain all the SEE mitigation strategies used in the RD53B chip, to report and analyze the heavy ions and proton tests results and to estimate the expected Single Event Upset (SEU) rates at the HL-LHC.

Single event effects on the RD53B pixel chip digital logic and on-chip CDR

“…The on-chip CDR is SET hardened with triplicated clock divider, a bang-bang phase detector and an optimized voltage-controlled oscillator (VCO) [2]. As a means of having a small pixel size and staying within power dissipation constraints, the chip has different protection schemes for its pixel and global configuration memory which prevents soft errors at two different levels of efficiency [3]. In case chip operation is critically affected by SEEs, a Clear command is implemented for fast clear of data buffers and state machines.…”