Single event effects on the RD53B pixel chip digital logic and on-chip CDR

Abstract

The RD53B chip for HL-LHC upgrades of ATLAS and CMS pixel detectors needs to provide reliable operation in a radiation hostile environment with inevitable Single Event Effects (SEE). To answer the challenge, substantial efforts are made to protect and evaluate the critical parts of the digital logic and to characterize the on-chip Clock and Data Recovery (CDR) circuit. The SEE sensitivity of the digital logic is evaluated by testing with both heavy-ions and protons. The on-chip CDR is characterized by measuring the SEE-induced phase shifts of its output clocks and their implication on the high-speed link stability.

Testing and characterisation of the prototype readout chip for the High-Luminosity LHC upgrade of the CMS Inner Tracker

“…Several single-event effects (SEE) testing campaigns have been performed with RD53B chips [15,16]. In general, it has been observed that in no case the ASIC ends up in a state which is unresponsive to input commands.…”