The RF noise in 0.18-m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for shortchannel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1 noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.

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We present a MOS Capacitance-Voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm ¾. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion and inversion.

The RF performance of deep-sub micron CMOS technologies was studied. Experimental data and a validated RF model have been used to evaluate trends in RF performance at bias conditions typical for RF design.

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