RF-CMOS Performance Trends

Woerlee, P.H.; Langevelde, R. van; Montree, A.H.; Klaassen, D.B.M.; Tiemeijer, L.F.; Vreede, P.W.H. de

doi:10.1109/essderc.2000.194843

Cited by 45 publications

(57 citation statements)

References 2 publications

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“…Even though the outcome depends on the boundary conditions chosen, the general trend is clear: noise is becoming a more significant limitation in future analog CMOS circuit design as device sizes ( and ) go down faster than goes up, thus reducing the number of carriers in a device ( (1) and [28]). Simulation-based analysis [2], supported by measurements, predicts a similar trend.…”

Section: Process Downscaling and Noisesupporting

confidence: 48%

“…This is because (a) independent noise sources (carriers) will produce total noise proportional to and (b) the current is also proportional to , resulting in the observed dependence of (2). Later it was shown by other experiments that the fluctuations observed by Hooge were mobility fluctuations .…”

Section: )mentioning

confidence: 88%

“…In the measurements, the traps reach their steady-state occupancy in an exponential fashion, indicating that the time constants do indeed change instantaneously with the bias of the device. 2 An alternate view (of a different RTS) is given in Fig. 5, which shows steady-state and transient behavior of an RTS.…”

Section: Transient Behavior Of Rts Noisementioning

confidence: 99%

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Low-Frequency Noise Phenomena in Switched MOSFETs

Wel

Klumperink

Kolhatkar

et al. 2007

IEEE J. Solid-State Circuits

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Abstract-In small-area MOSFETs widely used in analog and RF circuit design, low-frequency (LF) noise behavior is increasingly dominated by single-electron effects. In this paper, we review the limitations of current compact noise models which do not model such single-electron effects. We present measurement results that illustrate typical LF noise behavior in small-area MOSFETs, and a model based on Shockley-Read-Hall statistics to explain the behavior. Finally, we treat practical examples that illustrate the relevance of these effects to analog circuit design. To the analog circuit designer, awareness of these single-electron noise phenomena is crucial if optimal circuits are to be designed, especially since the effects can aid in low-noise circuit design if used properly, while they may be detrimental to performance if inadvertently applied.Index Terms-CMOS, flicker noise, large-signal excitation, lowfrequency noise, low-noise circuit design, MOSFET, noise reduction, RTS noise, switched biasing, 1 noise.

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Section: Process Downscaling and Noisesupporting

confidence: 48%

Section: )mentioning

confidence: 88%

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Low-Frequency Noise Phenomena in Switched MOSFETs

Wel

Klumperink

Kolhatkar

et al. 2007

IEEE J. Solid-State Circuits

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“…In order to study the linearity performance, analysis has been carried out in terms of higher order transconductance coefficients and device FOMs: V IP2 and V IP3 [24], third-order input intercept point (IIP3) [25] and 1-dB compression point, which has been obtained using drain current (I ds -V gs ) characteristics with channel length modulation (CLM) effect from sub-threshold to saturation region [26], and is defined as: , where, ε ox1 and ε ox2 are the Dielectric permittivity of lower and upper gate and t ox1 and t ox2 are the thickness of the lower and upper dielectric, respectively. Also, L eff is the effective channel length and; V dsx is the effective drain-source voltage and V gsx gives the smooth transition from strong to weak inversion, which is given as:…”

Section: Linearity-distortion Analysismentioning

confidence: 99%

Linearity-Distortion Analysis of GME-TRC MOSFET for High Performance and Wireless Applications

Malik¹,

Gupta²,

Chaujar³

et al. 2011

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: g m1 , g m2 , g m3 , and figure-of-merit (FOM) metrics; V IP2 , V IP3 , IIP3 and 1-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth (X j ) or negative junction depth (NJD) have been examined for GME-TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.

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“…The miniaturization of the metal oxide on semiconductor field effect transistor (MOSFET) has made complimentary metal oxide on semiconductor (CMOS) devices considerable radio frequency (RF) contenders where bipolars and high-electronmobility-transistors are traditionally dominant [1,2]. Strain engineering in deep submicrometer CMOS devices has further improved the high speed performance required for RF implementation [3].…”

Section: Introductionmentioning

confidence: 99%