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A novel in-plane double silicon-on-insulator optical MEMS accelerometer based on variable optical attenuator is presented. It is designed for micro-satellite navigation applications and it uses multimode waveguides integrated with MEMS providing a compact and reliable device.

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High performance photonic gyroscope microchips need ring resonators with high quality factors and low loss waveguides for enhanced accuracy. The industry trend is toward thin ring resonators with thick cladding layers above and below the waveguides. Thick cladding layers are typically required to ensure that the guided light's fields extending out from the waveguide are negligible before reaching any lossy material beyond the cladding layers. Otherwise, a significant portion of the field would be attenuated by the lossy material, thereby increasing the waveguide's overall propagation losses. However, thick cladding layers are undesirable from a process cost standpoint. We show that cavities etched below waveguides facilitate much thinner bottom cladding without increasing waveguide propagation losses. Commercial software computed the light within 100 nm thick and 40 nm thick waveguide designs as a function of their bottom cladding thickness. These simulations show that, with the underlying cavities, a 2 µm thick bottom cladding layer sufficiently confines the 100 nm thick waveguide's light. In the case of the 40 nm thick waveguide, this minimum cladding thickness was 3 µm. With these cavities, conventional bottom cladding thicknesses, normally 8 µm and 15 µm, respectively, are no longer necessary. 100 nm thick Si3N4 waveguides with 3 µm thick SiO2 bottom cladding layers were then fabricated, with and without cavities, alongside horizontally coupled coplanar ring resonators. Characterization of the fabricated structures show that the cavities reduce waveguide loss and improve ring resonator quality factor by a factor of three.

We use in-situ phosphorus-doped LPCVD (low-pressure chemical vapour deposition) polysilicon as a dopant source for silicon wafers. We used this technique for "3D doping", where poly-Si is deposited over structures patterned in silicon-on-insulator (SOI) wafers, which enables higher doping levels, as diffusion is performed through three surfaces rather than one. This technique can also be used for doping of unpatterned wafers, and we have derived a relation which estimates the doping level achieved with 3D doping using only 4-point probe measurements on blanket wafers. The advantage of this doping method compared to standard methods is that it does not require dedicated equipment and can be carried out using tools commonly available in a MEMS fab.