A novel 2-D analytical potential model of source and drain region along with channel for a fully depleted symmetric double gate junction less transistor is presented in this paper. The boundary conditions for channel potential along the channel length is taken considering source and drain region and boundary conditions for source and drain potential model are derived from channel longitudinal potential expression. The potential model is validated using TCAD simulations. A method for scale length determination is also presented. Scale length expression is obtained from the transverse electrostatic potential expression. Scale length variation with silicon layer thickness and gate oxide thickness is shown. The dependence of Scale length on the dielectric constant is also shown for the three dielectrics-"SiO 2 ", "Al 2 O 3 " and "HfO 2 ".
A novel method for reduction of off state leakage current in a symmetric double gate junctionless transistor (DG JLT) is presented in this paper. In this technique a layer of dielectric has been placed at centre of the JLT. As major portion of leakage current flows through the centre, placing a dielectric at the centre will reduce the leakage current to large extent. An analytical model of drain current and threshold voltage for the proposed structure is developed. The model is validated by comparing it with simulation results obtained from TCAD (Technology Computer Aided Design). The model is in close agreement with TCAD results. The model as well as simulation results show that the JLT with dielectric layer placed at the centre has lower subthreshold current compared to the conventional JLT.
This paper presents a method for determining the depletion width of single and double gate Junction Less transistor. By solving 1D Poisson's equation the depletion width expression is obtained. The variation of depletion width for both n-channel and p-channel device with doping concentration, gate voltage, drain to source voltage and dielectric constant of gate dielectric are shown.
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