A method for reduction of off state leakage current in symmetric DG JLT

Abstract

A novel method for reduction of off state leakage current in a symmetric double gate junctionless transistor (DG JLT) is presented in this paper. In this technique a layer of dielectric has been placed at centre of the JLT. As major portion of leakage current flows through the centre, placing a dielectric at the centre will reduce the leakage current to large extent. An analytical model of drain current and threshold voltage for the proposed structure is developed. The model is validated by comparing it with simulation results obtained from TCAD (Technology Computer Aided Design). The model is in close agreement with TCAD results. The model as well as simulation results show that the JLT with dielectric layer placed at the centre has lower subthreshold current compared to the conventional JLT.

Review–Silicon Based ISFETs: Architecture, Fabrication Process, Sensing Membrane, and Spatial Variation

“…[107][108][109][110][111][112][113] A higher sensitivity device is always desirable for both in-vivo and in-vitro systems. Several factors influence the sensitivity of a pH ISFET, including biorecognition layer and the transducer, 7 sensing channel material, 8 resident of hydroxyl group, measuring process and time, 114 processing parameters such as gas flow ratio, 115 fabrication process, 8,[114][115][116][117][118][119] pH sensor and interface unit, 117 parasitic effects (transconductance), 118 total surface-site density (N S ), 34,120,121 presence of oxygen on the surface and hydrogen content in silicon nitride sensitive films, 122 annealing conditions, 115,123 dielectric constant, 123,124 biasing regime of sensors and electrostatic screening of the analyte charges, 125 leakage current, 126,127 drift, 101,[128][129][130] depletion width, 131 capacitance of floating diffusion (FD), 132 scale length with gate oxide thickness. 133 In addition to the aforementioned factors, there are several challenges commonly encountered during experiments.…”

Off‐State Current Improvement of Double‐Gate Junctionless Field‐Effect Transistor by Modifying Central Potential

“…Beyond the excess of off‐state current, the applied gate voltage causes charges to build up close to the surface. [ 16–23 ]…”

“…Beyond the excess of off-state current, the applied gate voltage causes charges to build up close to the surface. [16][17][18][19][20][21][22][23] The body region of the device should remain fully depleted in the junctionless transistor for proper off-state of the device. To achieve this condition, the work function difference between the gate material and substrate must be high enough so that the resulting electric field can maintain the device in a fully depleted condition.…”