Dependence of Electrical Characteristics of Junctionless FET on Body Material

Talukdar, Angshumala; Raibaruah, Apurba Kumar; Sarma, Kaushik Chandra Deva

doi:10.1016/j.procs.2020.04.112

Cited by 8 publications

(16 citation statements)

References 18 publications

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“…BP has also been shown to go through a series of phase transitions and becomes superconductive at high pressures. [12] The band gap of BP has been predicted to increase with decreasing number of layers from 0.3 eV in bulk to 2 eV for single layer [10][11][12]. This is similar to MoS2, except that in BP the band gap remains direct for all number of layers [10].…”

Section: Introductionmentioning

confidence: 82%

“…Besides, JLFET are less sensitive in threshold voltages to variations with fabrication parameters and random dopant fluctuation effect [12]. Realizing these potential benefits several studies are reported on JLFET in the recent past for materials in their bulk state [11][12] demonstrating their merits. Thus, it is natural to anticipate that plugging the advantages of 2-D systems into the JLFET structures may produce even better device characteristics whose performance may meet the requirement set by IRDS for both HP and HD device.…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, JLFET is found to outperform conventional MOSFET in terms of subthreshold swing, intrinsic speed, power dissipation, and improved thermal budget [7][8][9][10][11]. Besides, JLFET are less sensitive in threshold voltages to variations with fabrication parameters and random dopant fluctuation effect [12]. Realizing these potential benefits several studies are reported on JLFET in the recent past for materials in their bulk state [11][12] demonstrating their merits.…”

Section: Introductionmentioning

confidence: 99%

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Performance of monolayer Black Phosphorus DG-JLFET: An ab initio study

Sanda

Dey²,

Dhar

2023

Preprint

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Two-dimensional materials are very promising for ultra-short channel future devices. This paper investigates, for the first time, the viability of the junction less transistors based on 2-D materials for future state-of-the-art technology nodes. Specifically, we investigate the performance of a Junction less monolayer black phosphorus (BP) FET (JLFET) with 12nm gate length using ab initio quantum transport simulations. The electrostatic control mechanism of the device and various intrinsic static and dynamic characteristics of the device are studied. The results reveal that BP JLFET performance can fulfill the benchmark requirement of International Roadmap for Devices and Systems (IRDS 2021) for 2028 in terms of HP and HD applications. Therefore, JLFET based on 2D materials can be a promising alternative for nano scale future device applications.

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Section: Introductionmentioning

confidence: 82%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Performance of monolayer Black Phosphorus DG-JLFET: An ab initio study

Sanda

Dey²,

Dhar

2023

Preprint

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“…Therefore, papers using Ge, GaAs, GaN, InGaAs, etc. as channel materials to increase the onto-off current ratio while reducing the channel resistance were also published [24][25]. As the device size decreases, the thickness of the gate oxide film must also decrease according to the scaling theory.…”

Section: Literature Reviewmentioning

confidence: 99%

Impact of Gate Metal Work-function for On-to-off Current Ratio and Threshold Voltage in Junctionless Gate-All-Around (GAA) MOSFET Stacked with SiO2 and High-k Dielectric

Jung¹

2023

IJETAE

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The relationship among the on-to-off current ratio, threshold voltage, and the gate metal work-function is investigated for a junctionless (JL) Gate-All-Around (GAA) MOSFET with a gate oxide film in which SiO2 and a high-k dielectric material are stacked. The JL structure works in the accumulation state, and the threshold voltage is defined as the gate voltage when the minimum potential in the channel becomes Fermi potential. The on-to-off current ratio Ion/Ioff is obtained by obtaining on-current Ion at the threshold voltage and off-current Ioff at the gate voltage of 0 V. As a result, if the channel doping concentration and silicon radius are increased to reduce the channel resistance, the on-to-off current ratio decreases along with the threshold voltage, but this problem can be solved through the increasing of the gate metal workfunction. In addition, even when the relative permittivity of the high-k dielectric is increased from 3.9 to 20, the gate metal work-function to maintain any on-to-off current ratio and threshold voltage is very slightly changed. Therefore it will be possible to improve the controllability of the gate by increasing the permittivity of the high-k dielectric without change in the work-function. The reduction of the channel resistance of the JL GAA MOSFET is possible with the stacked gate oxide while maintaining a reasonable on-to-off current ratio and threshold voltage by adjusting the gate metal work-function

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“…Unfortunately, conventional metal oxide semiconductor field effect transistors (MOSFETs) are not able to overcome SCEs and produce a stable and high current switching ratio (I ON /I OFF ), degraded SS, high DIBL, and highly sensitive electrical characteristics. For this, similar device structures such as Silicon on Insulator MOSFETs (SOI MOSFETs) for low SS and low leakage currents with less threshold voltages being applicable provided that the gate lengths are long [1][2][3][4] . But, Semiconductor device engineers are continuously investigating new devices and configurations to reduce SCEs and thus improve device performance for short…”

mentioning

confidence: 99%

Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications

Boggarapu

Lakshmi

2023

Sci Rep

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This work is intended to design a quadrature phase shift keying (QPSK) system starting from the device design, characterization and optimization which is then followed by the circuit level implementation and finally the system level configuration. Tunnel Field Effect Transistor (TFET) technology came into existence because of the inability of CMOS (Complementary Metal Oxide Semiconductor) to produce reduced leakage current (Ioff) in the subthreshold regime. With the effects of scaling and requirement of high doping concentrations, TFET is not capable to produce stable reduction in Ioff due to the variation in ON and OFF current. To improve the switching ratio of the current and to obtain good subthreshold swing (SS) by overcoming the limitations of junction TFET, a new device design is proposed for the first time in this work. A pocket double gate asymmetric Junction less TFET (poc-DG-AJLTFET) structure has been proposed in which uniform doping is used to eliminate the junctions and a pocket of length 2 nm made of Silicon–Germanium (SiGe) material has been introduced to improve the designed structure performance in the weak inversion region and increase the drive current (ION). The work function has been tuned to produce the best results for poc-DG-AJLTFET and with our proposed poc-DG-AJLTFET, effects of interface traps are eliminated as against conventional JLTFET structures. The notion that low-threshold voltage device yields high IOFF has been proved wrong with our poc-DG-AJLTFET design, as it produced low threshold voltage with lower IOFF which reduced the power dissipation. Numerical results show that drain induced barrier lowering (DIBL) of 2.75 mV/V is achieved which could be less than 35 times required for short channel effects to be minimum. In terms of gate to drain capacitance (Cgd), it is found that ~ 103 reduction which greatly improves device inertia to internal electrical interference. Also, improvement in transconductance is achieved by 104 times, 103 times improvement in ION/IOFF ratio, and 400 times higher unity gain cutoff-frequency (ft) which would be required by all communication systems. The Verilog models of the designed device are used to construct the leaf cells of quadrature phase shift keying (QPSK) system and the implemented QPSK system is taken as a key evaluator in the performance evaluation in terms of propagation delay and power consumption of poc-DG-AJLTFET in modern satellite communication systems.

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Dependence of Electrical Characteristics of Junctionless FET on Body Material

Cited by 8 publications

References 18 publications

Performance of monolayer Black Phosphorus DG-JLFET: An ab initio study

Performance of monolayer Black Phosphorus DG-JLFET: An ab initio study

Impact of Gate Metal Work-function for On-to-off Current Ratio and Threshold Voltage in Junctionless Gate-All-Around (GAA) MOSFET Stacked with SiO2 and High-k Dielectric

Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications

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