A six-band k⋅p model has been used to study the mobility of holes in Si inversion layers for different crystal orientations, for both compressive or tensile strain applied to the channel, and for a varying thickness of the Si layer. Scattering assisted by phonons and surface roughness has been accounted for, also comparing a full anisotropic model to an approximated isotropic treatment of the matrix elements. Satisfactory qualitative (and in several cases also quantitative) agreement is found between experimental data and theoretical results for the density and temperature dependence of the mobility for (001) surfaces, as well as for the dependence of the mobility on surface orientation [for the (011) and (111) surfaces]. Both compressive and tensile strain are found to enhance the mobility, while confinement effects result in a reduced hole mobility for a Si thickness ranging from 30 to 3 nm.
In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) below 10 nanometers (nm), as compared with current gate lengths in chips that are now about 50 nm. However, conventional scaling will no longer be sufficient to continue device performance by creating smaller transistors. Alternatives that are being pursued include new device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways. Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations. Here, we discuss challenges and possible solutions for continued silicon device performance trends down to the sub-10-nm gate regimes.
A tensile-strained Si layer was transferred to form an ultra-thin (<20 nm) strained Si directly on insulator (SSDOI) structure. MOSFETs were fabricated, and for the first time, electron and hole mobility enhancements were demonstrated on strained Si directly on insulator structures with no SiGe layer present under the strained Si CbaMek.
MotivationCarrier transport enhancement induced by strain has led to much interest in using strained Si to improve current drive in Si MOSFETs.
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