This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35µm CMOS-OPTO process. The chip implements a massively parallel focal-plane processing array which can output different simplified representations of the scene at very low power. The array is composed of pixel-level processing elements which carry out analog image processing concurrently with photosensing. These processing elements can be grouped into fully-programmable rectangular-shape areas by loading the appropiate interconnection patterns into the registers at the edge of the array. The targeted processing can be thus performed block-wise. Readout is done pixel-by-pixel in a random access fashion. On-chip 8b ADC is provided. The image processing primitives implemented by the chip, experimentally tested and fully functional, are scale space and Gaussian pyramid generation, fully-programmable multiresolution scene representation -including foveation -and block-wise energy-based scene representation. The power consumption associated to the capture, processing and A/D conversion of an image flow at 30fps, with full-frame processing but reduced frame size output, ranges from 2.7mW to 5.6mW, depending on the operation to be performed.

5This paper introduces a CMOS vision sensor chip in standard 0.18 µm CMOS technology for 6 Gaussian pyramid extraction. The Gaussian pyramid provides computer vision algorithms with scale 7 invariance, which permits to have the same response regardless of the distance of the scene to the 8 camera. The chip comprises 176 × 120 photosensors arranged into 88 × 60 processing elements (PEs). 9 The Gaussian pyramid is generated with a double-Euler switched-capacitor network. Every processing 10 element comprises four photodiodes, one 8-bit single-slope Analog to Digital Converter (ADC), one 11 Correlated Double Sampling (CDS) circuit, and 4 state capacitors with their corresponding switches 12 to implement the double-Euler switched-capacitor network. Every processing element occupies 44 × 13 44 µm 2 . Measurements from the chip are presented to assess the accuracy of the generated Gaussian 14 pyramid for visual tracking applications. Error levels are below 2% full scale output (FSO), thus making 15 the chip feasible for these applications. Also, energy cost is 26.5 nJ/px at 2.64 Mpx/s, thus outperforming 16 conventional solutions of imager plus microprocessor unit (MPU). 17 Keywords 18 The integration of camera systems for vision applications benefits from performing scene 22 analysis right at the sensor front-end. Such pre-processing may extract scene features and hence 23 reduce the number of data transmitted off the sensor chip for further processing. This is quite 24 a relevant characteristic because images contain many spare data, and data transmission and 25 storage consume significant energy and area. Also, pre-processing and reduced data transmission 26 result in increased throughput. Actually, pre-processing is smartly implemented in natural vision 27 systems [1], [2]; a fact that has motivated authors to explore architectures for CMOS imaging 28 front-ends with per-pixel processing circuitry [3]-[7]. These systems are recently making the 29 transition from academic proof-of-concept prototypes to industrial products [8].30Sensory-processing front-end chips with per-pixel processors operate typically as Single In-31 struction Multiple Data (SIMD) processors, namely, all processors run concurrently the same 32 operation on the data captured by the pixel photosensors, thus accelerating computation. Also, 33 mixed-signal per-pixel processors provide speed advantages with large energy efficiency [9], [10]. 34As a result, image sensors with embedded mixed-signal processors emerge as suitable candidates 35 for the front-end of vision systems with optimum SWaP (Size, Weight and Power) figures and 36 large throughput. Throughout the paper we will use the term CVIS (CMOS VIsion Sensors) to 37 refer to image front-end devices with embedded analysis capability and, we will retain the term 38 CIS (CMOS Image Sensors) for conventional image front-ends conceived to deliver just images. 39Major points hampering further development of CVIS-SIMD are: i) their outcome may not 40 be compatible with computer vision sof...

SUMMARYThis paper addresses the design and VLSI implementation of MOS-based RC networks capable of performing time-controlled Gaussian filtering. In these networks, all the resistors are substituted one by one by a single MOS transistor biased in the ohmic region. The design of this elementary transistor is carefully realized according to the value of the ideal resistor to be emulated. For a prescribed signal range, the MOSFET in triode region delivers an interval of instantaneous resistance values. We demonstrate that, for the elementary 2-node network, establishing the design equation at a particular point within this interval guarantees minimum error. This equation is then corroborated for networks of arbitrary size by analysing them from a stochastic point of view. Following the design methodology proposed, the error committed by a MOS-based grid when compared to its equivalent ideal RC network is, despite the intrinsic nonlinearities of the transistors, below 1% even under mismatch conditions of 10%. In terms of image processing, this error hardly affects the outcome, which is perceptually equivalent to that of the ideal network. These results, extracted from simulation, are verified in a prototype vision chip with QCIF resolution manufactured in the AMS 0.35µm CMOS-OPTO process. This prototype incorporates a focal-plane MOS-based RC network which performs fully-programmable Gaussian filtering.

Wireless sensor networks constitute a powerful technology particularly suitable for environmental monitoring. With regard to wildfires, they enable low-cost fine-grained surveillance of hazardous locations like wildland–urban interfaces. This paper presents work developed during the last 4 years targeting a vision-enabled wireless sensor network node for the reliable, early on-site detection of forest fires. The tasks carried out ranged from devising a robust vision algorithm for smoke detection to the design and physical implementation of a power-efficient smart imager tailored to the characteristics of such an algorithm. By integrating this smart imager with a commercial wireless platform, we endowed the resulting system with vision capabilities and radio communication. Numerous tests were arranged in different natural scenarios in order to progressively tune all the parameters involved in the autonomous operation of this prototype node. The last test carried out, involving the prescribed burning of a 95 × 20-m shrub plot, confirmed the high degree of reliability of our approach in terms of both successful early detection and a very low false-alarm rate.

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This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35µm CMOS-OPTO process. The chip implements a massively parallel focal-plane processing array which can output different simplified representations of the scene at very low power. The array is composed of pixel-level processing elements which carry out analog image processing concurrently with photosensing. These processing elements can be grouped into fully-programmable rectangular-shape areas by loading the appropiate interconnection patterns into the registers at the edge of the array. The targeted processing can be thus performed block-wise. Readout is done pixel-by-pixel in a random access fashion. On-chip 8b ADC is provided. The image processing primitives implemented by the chip, experimentally tested and fully functional, are scale space and Gaussian pyramid generation, fully-programmable multiresolution scene representation -including foveation -and block-wise energy-based scene representation. The power consumption associated to the capture, processing and A/D conversion of an image flow at 30fps, with full-frame processing but reduced frame size output, ranges from 2.7mW to 5.6mW, depending on the operation to be performed.

This paper describes a high dynamic range technique that compresses wide ranges of illuminations into the available signal range with a single exposure. An on-line analysis of the image histogram provides the sensor with the necessary feedback to dynamically accommodate changing illumination conditions. This adaptation is accomplished by properly weighing the influence of local and global illumination on each pixel response. The main advantages of this technique with respect to similar approaches previously reported are: i) standard active pixel sensor circuitry can be used to render the pixel values; ii) the resulting compressed image representation is ready either for readout or for early vision processing at the very focal plane without requiring any additional peripheral circuit block. Experimental results from a prototype smart image sensor achieving a dynamic range of 102dB are presented.

Abstract-This paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest points. The architecture is conceived for 3D IC technologies consisting of two layers (tiers) plus memory. The top tier includes sensing and processing circuitry aimed to perform Gaussian filtering and generate Gaussian pyramids in fully concurrent way. The circuitry in this tier operates in mixedsignal domain. It embeds in-pixel Correlated Double Sampling (CDS), a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel ADC (Analog to Digital Conversion). This tier can be further split into two for improved resolution; one containing the sensors and another containing a capacitor per sensor plus the mixed-signal processing circuitry. Regarding the bottom tier, it embeds digital circuitry entitled for the calculation of Harris, Hessian and DoG detectors. The overall system can hence be configured by the user to detect interest points by using the algorithm out of these three better suited to practical applications. The paper describes the different kind of algorithms featured and the circuitry employed at top and bottom tiers. The Gaussian pyramid is implemented with a Switched-Capacitor (SC) network in less than 50 µs, outperforming more conventional solutions.