All‐MOS implementation of RC networks for time‐controlled Gaussian spatial filtering

Abstract

SUMMARYThis paper addresses the design and VLSI implementation of MOS-based RC networks capable of performing time-controlled Gaussian filtering. In these networks, all the resistors are substituted one by one by a single MOS transistor biased in the ohmic region. The design of this elementary transistor is carefully realized according to the value of the ideal resistor to be emulated. For a prescribed signal range, the MOSFET in triode region delivers an interval of instantaneous resistance values. We demonstrate that, for the elementary 2-node network, establishing the design equation at a particular point within this interval guarantees minimum error. This equation is then corroborated for networks of arbitrary size by analysing them from a stochastic point of view. Following the design methodology proposed, the error committed by a MOS-based grid when compared to its equivalent ideal RC network is, despite the intrinsic nonlinearities of the transistors, below 1% even under mismatch conditions of 10%. In terms of image processing, this error hardly affects the outcome, which is perceptually equivalent to that of the ideal network. These results, extracted from simulation, are verified in a prototype vision chip with QCIF resolution manufactured in the AMS 0.35µm CMOS-OPTO process. This prototype incorporates a focal-plane MOS-based RC network which performs fully-programmable Gaussian filtering.

Ultralow-Power Processing Array for Image Enhancement and Edge Detection

“…The efficiency of the MOS-based RC network was previously mentioned and experimentally proved in [6]. The energy cost of the digital cells included now, with an order of magnitude of tens of nW/MHz at most, is also really small for typical frame rates of most vision applications.…”

“…We demonstrated in [6] that an accurate approximation of an ideal RC network can be obtained by substituting every resistor by a MOS transistor biased in the ohmic region. Moreover, the value of the pixels can be easily mapped to the initial conditions of the capacitors and, without any additional energy contribution, the network will carry out isotropic filtering.…”

“…Consider a signal range of [0.75V,1.5V] for the pixel values. This range is chosen according to the criteria described in [6]. Bear in mind that the pixels are represented by the voltages V ij , which in turn constitute the inputs of the voltage comparators across the network.…”

“…The value of the elementary capacitor of the RC network simulated is 1pF whereas the dimensions of the elementary MOS resistor are 0.15/1. According to the design methodology described in [6], these elements render a time constant τ = 118ns. Consequently, the width of the Gaussian filter applied is σ = 2t/τ = 0.92.…”

“…We present a massively parallel processing array for image enhancement and edge detection designed for the 0.13µm 1.5V standard CMOS base process of the TSV stack commercialized by Tezzaron Semiconductor. The backbone of the array is a MOSbased RC network carrying out isotropic diffusion [6]. On this, we incorporate now a low-power time-controlled voltage comparator between neighboring nodes.…”