FLIP-Q: A QCIF Resolution Focal-Plane Array for Low-Power Image Processing

Abstract

This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35µm CMOS-OPTO process. The chip implements a massively parallel focal-plane processing array which can output different simplified representations of the scene at very low power. The array is composed of pixel-level processing elements which carry out analog image processing concurrently with photosensing. These processing elements can be grouped into fully-programmable rectangular-shape areas by loading the appropiate interconnection patterns into the registers at the edge of the array. The targeted processing can be thus performed block-wise. Readout is done pixel-by-pixel in a random access fashion. On-chip 8b ADC is provided. The image processing primitives implemented by the chip, experimentally tested and fully functional, are scale space and Gaussian pyramid generation, fully-programmable multiresolution scene representation -including foveation -and block-wise energy-based scene representation. The power consumption associated to the capture, processing and A/D conversion of an image flow at 30fps, with full-frame processing but reduced frame size output, ranges from 2.7mW to 5.6mW, depending on the operation to be performed.

Distributed mixed-signal architecture for programmable smart image sensors

“…During the last decade several smart vision sensors have been designed in standard CIS technology [1,[3][4][5][6][7][8][9][10][11][12][13][14][15]. The increasing resolutions and frame rates result in a large data transfer between the imaging array and the processing unit.…”

“…On the other hand, analog processing needs no in-pixel ADC, and would consume less power. Therefore, and considering our application, we focus here on analog implementation of common processing tasks such as edge detection using spatial convolution [1,3], difference of averaged images [4] and neighbours comparison [5] ; motion detection using temporal difference [1,5] ; or image enhancement [1,6].…”

“…On the other hand, programmable VSoCs have been proposed in [1,6,10], but with only in-pixel processing circuits and thus they suffer from very low fill factor (e.g. 5,4% in [10]).…”

Focal-Plane Sensing-Processing: A Power-Efficient Approach for the Implementation of Privacy-Aware Networked Visual Sensors

“…To this end, we make use of the squarer experimentally tested and reported in [48]. Thus, by precharging the capacitor holding V SQ ij to V DD and exploiting its discharge for a short period of time through the transistor M SQ working in the saturation region, the value of the pixel square can be computed.…”

A 176×120 pixel CMOS vision chip for Gaussian filtering with massivelly Parallel CDS and A/D-conversion

“…Low-level image tasks like convolution-type operations as Gaussian pyramids are better suited for a Single Instruction Multiple Data (SIMD) architecture with a Processing Element (PE) per pixel. The Gaussian filtering is naturally performed by both a resistive-capacitor (RC) grid, or a switched-capacitor (SC) network [2], [3]. These solutions outperform some other paradigms like those based on cellular non-linear networks [4].…”