Objectives RF and ACPA are used as diagnostic tools and their presence has been associated with clinical response to some biologic DMARDs (bDMARDs) in RA. This study compared the impact of seropositivity on drug discontinuation and effectiveness of bDMARDs in patients with RA, using head-to-head comparisons in a real-world setting. Methods We conducted a pooled analysis of 16 observational RA registries. Inclusion criteria were a diagnosis of RA, initiation of treatment with rituximab (RTX), abatacept (ABA), tocilizumab (TCZ) or TNF inhibitors (TNFis) and available information on RF and/or ACPA status. Drug discontinuation was analysed using Cox regression, including drug, seropositivity, their interaction, adjusting for concomitant and past treatments and patient and disease characteristics and accounting for country and calendar year of bDMARD initiation. Effectiveness was analysed using the Clinical Disease Activity Index evolution over time. Results Among the 27 583 eligible patients, the association of seropositivity with drug discontinuation differed across bDMARDs (P for interaction <0.001). The adjusted hazard ratios for seropositive compared with seronegative patients were 1.01 (95% CI 0.95, 1.07) for TNFis, 0.89 (0.78, 1.02)] for TCZ, 0.80 (0.72, 0.88) for ABA and 0.70 (0.59, 0.84) for RTX. Adjusted differences in remission and low disease activity rates between seropositive and seronegative patients followed the same pattern, with no difference in TNFis, a small difference in TCZ, a larger difference in ABA and the largest difference in RTX (Lundex remission difference +5.9%, low disease activity difference +11.6%). Conclusion Seropositivity was associated with increased effectiveness of non-TNFi bDMARDs, especially RTX and ABA, but not TNFis.

5This paper introduces a CMOS vision sensor chip in standard 0.18 µm CMOS technology for 6 Gaussian pyramid extraction. The Gaussian pyramid provides computer vision algorithms with scale 7 invariance, which permits to have the same response regardless of the distance of the scene to the 8 camera. The chip comprises 176 × 120 photosensors arranged into 88 × 60 processing elements (PEs). 9 The Gaussian pyramid is generated with a double-Euler switched-capacitor network. Every processing 10 element comprises four photodiodes, one 8-bit single-slope Analog to Digital Converter (ADC), one 11 Correlated Double Sampling (CDS) circuit, and 4 state capacitors with their corresponding switches 12 to implement the double-Euler switched-capacitor network. Every processing element occupies 44 × 13 44 µm 2 . Measurements from the chip are presented to assess the accuracy of the generated Gaussian 14 pyramid for visual tracking applications. Error levels are below 2% full scale output (FSO), thus making 15 the chip feasible for these applications. Also, energy cost is 26.5 nJ/px at 2.64 Mpx/s, thus outperforming 16 conventional solutions of imager plus microprocessor unit (MPU). 17 Keywords 18 The integration of camera systems for vision applications benefits from performing scene 22 analysis right at the sensor front-end. Such pre-processing may extract scene features and hence 23 reduce the number of data transmitted off the sensor chip for further processing. This is quite 24 a relevant characteristic because images contain many spare data, and data transmission and 25 storage consume significant energy and area. Also, pre-processing and reduced data transmission 26 result in increased throughput. Actually, pre-processing is smartly implemented in natural vision 27 systems [1], [2]; a fact that has motivated authors to explore architectures for CMOS imaging 28 front-ends with per-pixel processing circuitry [3]-[7]. These systems are recently making the 29 transition from academic proof-of-concept prototypes to industrial products [8].30Sensory-processing front-end chips with per-pixel processors operate typically as Single In-31 struction Multiple Data (SIMD) processors, namely, all processors run concurrently the same 32 operation on the data captured by the pixel photosensors, thus accelerating computation. Also, 33 mixed-signal per-pixel processors provide speed advantages with large energy efficiency [9], [10]. 34As a result, image sensors with embedded mixed-signal processors emerge as suitable candidates 35 for the front-end of vision systems with optimum SWaP (Size, Weight and Power) figures and 36 large throughput. Throughout the paper we will use the term CVIS (CMOS VIsion Sensors) to 37 refer to image front-end devices with embedded analysis capability and, we will retain the term 38 CIS (CMOS Image Sensors) for conventional image front-ends conceived to deliver just images. 39Major points hampering further development of CVIS-SIMD are: i) their outcome may not 40 be compatible with computer vision sof...

In scale-space filtering signals are represented at several scales, each conveying different details of the original signal. Every new scale is the result of a smoothing operator on a former scale. In image processing, scale-space filtering is widely used in feature extractors as the Scale-Invariant Feature Transform (SIFT) algorithm. RC networks are posed as valid scale-space generators in focal-plane processing. Switchedcapacitor networks are another alternative, as different topologies and switching rate offer a great flexibility. This work examines the parallel and the bilinear implementations as two different switched-capacitor network topologies for scale-space filtering. The paper assesses the validity of both topologies as scale-space generators in focal-plane processing through object detection with the SIFT algorithm.

Abstract-This paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest points. The architecture is conceived for 3D IC technologies consisting of two layers (tiers) plus memory. The top tier includes sensing and processing circuitry aimed to perform Gaussian filtering and generate Gaussian pyramids in fully concurrent way. The circuitry in this tier operates in mixedsignal domain. It embeds in-pixel Correlated Double Sampling (CDS), a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel ADC (Analog to Digital Conversion). This tier can be further split into two for improved resolution; one containing the sensors and another containing a capacitor per sensor plus the mixed-signal processing circuitry. Regarding the bottom tier, it embeds digital circuitry entitled for the calculation of Harris, Hessian and DoG detectors. The overall system can hence be configured by the user to detect interest points by using the algorithm out of these three better suited to practical applications. The paper describes the different kind of algorithms featured and the circuitry employed at top and bottom tiers. The Gaussian pyramid is implemented with a Switched-Capacitor (SC) network in less than 50 µs, outperforming more conventional solutions.

This paper conveys a proof-of-concept chip for Gaussian pyramid generation for image feature detectors. Gaussian filtering and image resizing are performed with a switchedcapacitor (SC) network. The chip is conceived as the mapping of a CMOS-3D architecture for feature detectors onto a conventional technology, with some functionality removed, and the corresponding area overhead with respect to a CMOS-3D architecture, but preserving masivelly parallel Correlated Double Sampling (CDS) and A/D conversion. The chip has been fabricated on a die of 5×5 mm 2 with 0.18 µm CMOS technology, achieving an array of 176×120 sensing elements (pixels). The pixels are arranged in Processing Elements (PEs). Every PE comprises four photodiodes, four SC nodes, one CDS circuit, and local circuitry for one ADC. Every PE occupies an area of 44×44 µm 2. The chip senses an image and computes the Gaussian pyramid with an average power consumption lower than 75 nW/pixel at 30 frames/s.