Low-Power CMOS Vision Sensor for Gaussian Pyramid Extraction

Abstract

5This paper introduces a CMOS vision sensor chip in standard 0.18 µm CMOS technology for 6 Gaussian pyramid extraction. The Gaussian pyramid provides computer vision algorithms with scale 7 invariance, which permits to have the same response regardless of the distance of the scene to the 8 camera. The chip comprises 176 × 120 photosensors arranged into 88 × 60 processing elements (PEs). 9 The Gaussian pyramid is generated with a double-Euler switched-capacitor network. Every processing 10 element comprises four photodiodes, one 8-bit single-slope Analog to Digital Converter (ADC), one 11 Correlated Double Sampling (CDS) circuit, and 4 state capacitors with their corresponding switches 12 to implement the double-Euler switched-capacitor network. Every processing element occupies 44 × 13 44 µm 2 . Measurements from the chip are presented to assess the accuracy of the generated Gaussian 14 pyramid for visual tracking applications. Error levels are below 2% full scale output (FSO), thus making 15 the chip feasible for these applications. Also, energy cost is 26.5 nJ/px at 2.64 Mpx/s, thus outperforming 16 conventional solutions of imager plus microprocessor unit (MPU). 17 Keywords 18 The integration of camera systems for vision applications benefits from performing scene 22 analysis right at the sensor front-end. Such pre-processing may extract scene features and hence 23 reduce the number of data transmitted off the sensor chip for further processing. This is quite 24 a relevant characteristic because images contain many spare data, and data transmission and 25 storage consume significant energy and area. Also, pre-processing and reduced data transmission 26 result in increased throughput. Actually, pre-processing is smartly implemented in natural vision 27 systems [1], [2]; a fact that has motivated authors to explore architectures for CMOS imaging 28 front-ends with per-pixel processing circuitry [3]-[7]. These systems are recently making the 29 transition from academic proof-of-concept prototypes to industrial products [8].30Sensory-processing front-end chips with per-pixel processors operate typically as Single In-31 struction Multiple Data (SIMD) processors, namely, all processors run concurrently the same 32 operation on the data captured by the pixel photosensors, thus accelerating computation. Also, 33 mixed-signal per-pixel processors provide speed advantages with large energy efficiency [9], [10]. 34As a result, image sensors with embedded mixed-signal processors emerge as suitable candidates 35 for the front-end of vision systems with optimum SWaP (Size, Weight and Power) figures and 36 large throughput. Throughout the paper we will use the term CVIS (CMOS VIsion Sensors) to 37 refer to image front-end devices with embedded analysis capability and, we will retain the term 38 CIS (CMOS Image Sensors) for conventional image front-ends conceived to deliver just images. 39Major points hampering further development of CVIS-SIMD are: i) their outcome may not 40 be compatible with computer vision sof...

An Ultra-Low-Energy Analog Comparator for A/D Converters in CMOS Image Sensors

“…The human eye is not sensitive to nonlinearity of an image sensor in terms of gradient of gray, and, therefore, it is not an issue for most applications. For vision chips, for example, the most important is a high processing efficiency, while image quality is less critical [2,8,15,17,18].…”

In‐pixel analog memories for a pixel‐based background subtraction algorithm on CMOS vision sensors

“…3 However, the Gaussian blurring is kept as this is a critical step in background subtraction algorithms and feasible in the analog domain. 5,17 The second change made with respect to the original PBAS algorithm was to avoid the use of image gradient at pixel values comparison. Also, the neighborhood interaction was reduced from 8-connectivity to 4-connectivity, and the minimum number of background samples needed was also assessed to limit the number of in-pixel memories.…”

“…In terms of the algorithm itself, the PBAS equations were also simplified towards a more lineal model. In particular, the background model update mechanism was modified to avoid divisions, replacing (4) by (5), where p(x i ) is the inverse of T(x i ) and p dec and p inc are fixed parameters. In our approach, d(x i ) is in the [0,1] range.…”

“…The memory overhead is even more critical on CMOS vision sensors or focal plane processing with a per-pixel approach. 5,6 This has caused us to introduce a hardware-oriented PBAS algorithm, 7 the so-called HO-PBAS, leading to less per-pixel memories while keeping similar performance metrics to the original PBAS when assessed over the CDNET14 database.…”

“…Although there are many examples of CMOS vision sensors in the literature, see, for instance, Suárez et al 5 and references therein, we focus on some recent implementations and their in-pixel memory topologies.…”