A 176×120 pixel CMOS vision chip for Gaussian filtering with massivelly Parallel CDS and A/D-conversion

Abstract

This paper conveys a proof-of-concept chip for Gaussian pyramid generation for image feature detectors. Gaussian filtering and image resizing are performed with a switchedcapacitor (SC) network. The chip is conceived as the mapping of a CMOS-3D architecture for feature detectors onto a conventional technology, with some functionality removed, and the corresponding area overhead with respect to a CMOS-3D architecture, but preserving masivelly parallel Correlated Double Sampling (CDS) and A/D conversion. The chip has been fabricated on a die of 5×5 mm 2 with 0.18 µm CMOS technology, achieving an array of 176×120 sensing elements (pixels). The pixels are arranged in Processing Elements (PEs). Every PE comprises four photodiodes, four SC nodes, one CDS circuit, and local circuitry for one ADC. Every PE occupies an area of 44×44 µm 2. The chip senses an image and computes the Gaussian pyramid with an average power consumption lower than 75 nW/pixel at 30 frames/s.

Gaussian pyramid extraction with a CMOS vision sensor

“…Each PE is shorted to two 8-bit registers in their assigned frame buffer. This permits to read out pixels outside the chip as they are being read in from the PE array [6]. Fig.…”

Distributed mixed-signal architecture for programmable smart image sensors

“…During the last decade several smart vision sensors have been designed in standard CIS technology [1,[3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. The increasing resolutions and frame rates result in a large data transfer between the imaging array and the processing unit.…”

“…On the other hand, the concept of macropixels can be implemented in hardware by mutualizing in-matrix circuitry for the block of pixels instead of repeating it in every pixel. Suárez et al [15] proposed such a hardware macropixel: 4 photodetectors share an amplifier and an ADC. A solution for Gaussian filtering is also implemented in [16], but it relies on a full resolution switched-capacitor network which does not really take advantage of the macropixel concept.…”

Distributed mixed-signal architecture for programmable smart image sensors

“…During the last decade several smart vision sensors have been designed in standard CIS technology [1,[3][4][5][6][7][8][9][10][11][12][13][14][15]. The increasing resolutions and frame rates result in a large data transfer between the imaging array and the processing unit.…”

“…On the other hand, the concept of macropixels can be implemented in hardware by mutualizing in-matrix circuitry for the block of pixels instead of repeating it in every pixel. Suárez et al [13] proposed such a hardware macropixel: 4 photodetectors share an amplifier and an ADC. A solution for Gaussian filtering is also implemented in [13], but it relies on a full resolution switched-capacitor network which does not really take advantage of the macropixel concept.…”