Gaussian pyramid extraction with a CMOS vision sensor

Abstract

This paper addresses a CMOS vision sensor with 176 × 120 pixels in standard 0.18 µm CMOS technology that computes the Gaussian pyramid. The Gaussian pyramid is extracted with a double-Euler switched-capacitor network, giving RMSE errors below 1.2% of full-scale value. The chip provides a Gaussian pyramid of 3 octaves with 6 scales each with an energy cost of 26.5 nJ at 2.64 Mpx/s.

Implementation of Scale Invariant Feature Transform detector on FPGA for low‐power wearable devices for prostheses control

“…Furthermore, the FPGA has a lower energy consumption than the Intel Xeon E5-2620 server CPU, and the GPUs. FPGA based solutions also support higher image resolution compared to CMOS Vision Sensor 21,22 implementation. and the size of the processed image can be modified similarly to the CPU implementations.…”

“…The most computationally intensive operation in SIFT keypoint extraction is the computation of the Gaussian pyramids as it requires multiplication of coefficients of Gaussian filters with scale-space images. For this step, an analog solution is developed by Rodríguez-V azquez et al 21,22 where the Gaussian pyramid is computed by an analog CMOS circuit and exhibits very low dissipated power. One of the advantage of the inherent parallel processing is the high computational power of the analog VLSI implementations.…”

“…However, the size of the array is small. [21][22][23] In Su arez et al 22 the analog sensor/processor implementation has 88x60 processing elements, and each processing element has four photodiodes. The computation unit is connected to the vision sensor unit of the camera.…”