CMOS-3D Smart Imager Architectures for Feature Detection

Abstract

Abstract-This paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest points. The architecture is conceived for 3D IC technologies consisting of two layers (tiers) plus memory. The top tier includes sensing and processing circuitry aimed to perform Gaussian filtering and generate Gaussian pyramids in fully concurrent way. The circuitry in this tier operates in mixedsignal domain. It embeds in-pixel Correlated Double Sampling (CDS), a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel ADC (Analog to Digital Conversion). This tier can be further split into two for improved resolution; one containing the sensors and another containing a capacitor per sensor plus the mixed-signal processing circuitry. Regarding the bottom tier, it embeds digital circuitry entitled for the calculation of Harris, Hessian and DoG detectors. The overall system can hence be configured by the user to detect interest points by using the algorithm out of these three better suited to practical applications. The paper describes the different kind of algorithms featured and the circuitry employed at top and bottom tiers. The Gaussian pyramid is implemented with a Switched-Capacitor (SC) network in less than 50 µs, outperforming more conventional solutions.

Gaussian Pyramid: Comparative Analysis of Hardware Architectures

“…Due to the significance of the GP as a fundamental processing primitive in computer vision, numerous non-conventional approaches aiming at boosting its hardware performance have also been reported [12], [13], [16]- [20]. Among them, mixedsignal focal-plane sensing-processing [12], [13], [16], [17] stands out as the best approach in terms of parallelization and energy efficiency.…”

“…Among them, mixedsignal focal-plane sensing-processing [12], [13], [16], [17] stands out as the best approach in terms of parallelization and energy efficiency. Additional circuitry is incorporated per pixel, usually connected to its counterpart at neighboring pixels, in order to concurrently process the image sensed by photo-sensitive circuit elements.…”

“…However, the functional primitive underlying GP calculation is rather simple -just diffusions across the scene plane are needed. Diffusions can be implemented by embedding simple mixed-signal circuits at pixel level, as done for instance in [12], [13]. Actually, results in [13] demonstrate orders of magnitude of improvement in throughput and energy consumption when compared to architectures using conventional, data-centric, sensors.…”

Image Feature Extraction Acceleration

“…This chip was conceived, from the very beginning, for implementation in 3-D integration technologies [40]. Unfortunately, these technologies are not mature enough yet for reliable fabrication.…”

Form factor improvement of smart-pixels for vision sensors through 3-D vertically-integrated technologies

“…This is actually the very domain of analog and mixedsignal circuits [8][27] [27]. 3D sensor architectures for the extraction of features and the calculation of interest points within imagers have been previously proposed by the authors in [27] and [28]. Both architectures rely on the implementation of Gaussian filtering at the sensory plane and the calculation of Gaussian pyramids thereof.…”